diff options
Diffstat (limited to 'cpu/o3')
| -rw-r--r-- | cpu/o3/cpu.cc | 40 | ||||
| -rw-r--r-- | cpu/o3/fetch_impl.hh | 3 | ||||
| -rw-r--r-- | cpu/o3/inst_queue.hh | 4 | ||||
| -rw-r--r-- | cpu/o3/inst_queue_impl.hh | 7 | ||||
| -rw-r--r-- | cpu/o3/lsq_unit.hh | 3 | ||||
| -rw-r--r-- | cpu/o3/lsq_unit_impl.hh | 5 | ||||
| -rw-r--r-- | cpu/o3/rename.hh | 2 | ||||
| -rw-r--r-- | cpu/o3/rename_impl.hh | 8 |
8 files changed, 65 insertions, 7 deletions
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 0025d4144..88de6c746 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -599,8 +599,11 @@ FullO3CPU<Impl>::activateContext(int tid, int delay) // Be sure to signal that there's some activity so the CPU doesn't // deschedule itself. activityRec.activity(); + +#if FULL_SYSTEM if (thread[tid]->quiesceEvent && thread[tid]->quiesceEvent->scheduled()) thread[tid]->quiesceEvent->deschedule(); +#endif fetch.wakeFromQuiesce(); @@ -671,6 +674,8 @@ template <class Impl> void FullO3CPU<Impl>::switchOut(Sampler *_sampler) { + DPRINTF(FullCPU, "Switching out\n"); + BaseCPU::switchOut(_sampler); sampler = _sampler; switchCount = 0; fetch.switchOut(); @@ -694,6 +699,41 @@ FullO3CPU<Impl>::signalSwitched() rename.doSwitchOut(); commit.doSwitchOut(); instList.clear(); + +#ifndef NDEBUG + PhysRegIndex renamed_reg; + // First loop through the integer registers. + for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { + renamed_reg = renameMap[0].lookup(i); + assert(renamed_reg == commitRenameMap[0].lookup(i)); + + DPRINTF(FullCPU, "FullCPU: Checking if register %i is ready.\n", + renamed_reg); + + assert(scoreboard.getReg(renamed_reg)); + } + + // Then loop through the floating point registers. + for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { + renamed_reg = renameMap[0].lookup(i + AlphaISA::FP_Base_DepTag); + assert(renamed_reg == commitRenameMap[0].lookup(i + AlphaISA::FP_Base_DepTag)); + + DPRINTF(FullCPU, "FullCPU: Checking if register %i is ready.\n", + renamed_reg); + + assert(scoreboard.getReg(renamed_reg)); + } + + for (int i = 0; i < AlphaISA::NumMiscRegs; ++i) { + renamed_reg = i + ((Params *)params)->numPhysFloatRegs + ((Params *)params)->numPhysIntRegs; + + DPRINTF(FullCPU, "FullCPU: Checking if register %i is ready.\n", + renamed_reg); + + assert(scoreboard.getReg(renamed_reg)); + } +#endif + while (!removeList.empty()) { removeList.pop(); } diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index cc09c4a41..7a3292dbe 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -391,6 +391,7 @@ DefaultFetch<Impl>::takeOverFrom() wroteToTimeBuffer = false; _status = Inactive; switchedOut = false; + interruptPending = false; branchPred.takeOverFrom(); } @@ -469,7 +470,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid unsigned flags = 0; #endif // FULL_SYSTEM - if (interruptPending && flags == 0) { + if (isSwitchedOut() || (interruptPending && flags == 0)) { // Hold off fetch from getting new instructions while an interrupt // is pending. return false; diff --git a/cpu/o3/inst_queue.hh b/cpu/o3/inst_queue.hh index 80cd71f0d..e96fbc667 100644 --- a/cpu/o3/inst_queue.hh +++ b/cpu/o3/inst_queue.hh @@ -474,11 +474,11 @@ class InstructionQueue Stats::Scalar<> iqSquashedNonSpecRemoved; /** Distribution of number of instructions in the queue. */ - Stats::VectorDistribution<> queueResDist; +// Stats::VectorDistribution<> queueResDist; /** Distribution of the number of instructions issued. */ Stats::Distribution<> numIssuedDist; /** Distribution of the cycles it takes to issue an instruction. */ - Stats::VectorDistribution<> issueDelayDist; +// Stats::VectorDistribution<> issueDelayDist; /** Number of times an instruction could not be issued because a * FU was busy. diff --git a/cpu/o3/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh index 72cb0d708..b6b06ca77 100644 --- a/cpu/o3/inst_queue_impl.hh +++ b/cpu/o3/inst_queue_impl.hh @@ -230,7 +230,7 @@ InstructionQueue<Impl>::regStats() .name(name() + ".iqSquashedNonSpecRemoved") .desc("Number of squashed non-spec instructions that were removed") .prereq(iqSquashedNonSpecRemoved); - +/* queueResDist .init(Num_OpClasses, 0, 99, 2) .name(name() + ".IQ:residence:") @@ -240,6 +240,7 @@ InstructionQueue<Impl>::regStats() for (int i = 0; i < Num_OpClasses; ++i) { queueResDist.subname(i, opClassStrings[i]); } +*/ numIssuedDist .init(0,totalWidth,1) .name(name() + ".ISSUE:issued_per_cycle") @@ -268,7 +269,7 @@ InstructionQueue<Impl>::regStats() // // How long did instructions for a particular FU type wait prior to issue // - +/* issueDelayDist .init(Num_OpClasses,0,99,2) .name(name() + ".ISSUE:") @@ -281,7 +282,7 @@ InstructionQueue<Impl>::regStats() subname << opClassStrings[i] << "_delay"; issueDelayDist.subname(i, subname.str()); } - +*/ issueRate .name(name() + ".ISSUE:rate") .desc("Inst issue rate") diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh index fe174a97d..1db6dc02d 100644 --- a/cpu/o3/lsq_unit.hh +++ b/cpu/o3/lsq_unit.hh @@ -382,6 +382,9 @@ class LSQUnit { * ignored due to the instruction already being squashed. */ Stats::Scalar<> lsqIgnoredResponses; + /** Tota number of memory ordering violations. */ + Stats::Scalar<> lsqMemOrderViolation; + /** Total number of squashed stores. */ Stats::Scalar<> lsqSquashedStores; diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh index 5cc3078f8..7086c381e 100644 --- a/cpu/o3/lsq_unit_impl.hh +++ b/cpu/o3/lsq_unit_impl.hh @@ -144,6 +144,10 @@ LSQUnit<Impl>::regStats() .name(name() + ".ignoredResponses") .desc("Number of memory responses ignored because the instruction is squashed"); + lsqMemOrderViolation + .name(name() + ".memOrderViolation") + .desc("Number of memory ordering violations"); + lsqSquashedStores .name(name() + ".squashedStores") .desc("Number of stores squashed"); @@ -495,6 +499,7 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) // A load incorrectly passed this store. Squash and refetch. // For now return a fault to show that it was unsuccessful. memDepViolator = loadQueue[load_idx]; + ++lsqMemOrderViolation; return genMachineCheckFault(); } diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh index 4912431ad..5769dbd37 100644 --- a/cpu/o3/rename.hh +++ b/cpu/o3/rename.hh @@ -411,6 +411,8 @@ class DefaultRename /** The maximum skid buffer size. */ unsigned skidBufferMax; + PhysRegIndex maxPhysicalRegs; + /** Enum to record the source of a structure full stall. Can come from * either ROB, IQ, LSQ, and it is priortized in that order. */ diff --git a/cpu/o3/rename_impl.hh b/cpu/o3/rename_impl.hh index 93f5b3504..49627e3d4 100644 --- a/cpu/o3/rename_impl.hh +++ b/cpu/o3/rename_impl.hh @@ -40,7 +40,8 @@ DefaultRename<Impl>::DefaultRename(Params *params) commitToRenameDelay(params->commitToRenameDelay), renameWidth(params->renameWidth), commitWidth(params->commitWidth), - numThreads(params->numberOfThreads) + numThreads(params->numberOfThreads), + maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) { _status = Inactive; @@ -283,6 +284,11 @@ DefaultRename<Impl>::doSwitchOut() // Put the renamed physical register back on the free list. freeList->addReg(hb_it->newPhysReg); + // Be sure to mark its register as ready if it's a misc register. + if (hb_it->newPhysReg >= maxPhysicalRegs) { + scoreboard->setReg(hb_it->newPhysReg); + } + historyBuffer[i].erase(hb_it++); } insts[i].clear(); |