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-rw-r--r--cpu/o3/2bit_local_pred.hh2
-rw-r--r--cpu/o3/alpha_cpu.hh7
-rw-r--r--cpu/o3/alpha_cpu_impl.hh22
-rw-r--r--cpu/o3/alpha_dyn_inst.hh33
-rw-r--r--cpu/o3/alpha_dyn_inst_impl.hh2
-rw-r--r--cpu/o3/alpha_impl.hh5
-rw-r--r--cpu/o3/bpred_unit_impl.hh2
-rw-r--r--cpu/o3/btb.cc2
-rw-r--r--cpu/o3/btb.hh2
-rw-r--r--cpu/o3/commit.hh1
-rw-r--r--cpu/o3/commit_impl.hh2
-rw-r--r--cpu/o3/cpu.cc18
-rw-r--r--cpu/o3/cpu.hh5
-rw-r--r--cpu/o3/decode.hh4
-rw-r--r--cpu/o3/fetch.hh5
-rw-r--r--cpu/o3/fetch_impl.hh12
-rw-r--r--cpu/o3/free_list.hh2
-rw-r--r--cpu/o3/iew.hh1
-rw-r--r--cpu/o3/iew_impl.hh2
-rw-r--r--cpu/o3/ras.hh2
-rw-r--r--cpu/o3/regfile.hh300
-rw-r--r--cpu/o3/rename.hh3
-rw-r--r--cpu/o3/rename_map.hh4
-rw-r--r--cpu/o3/rob.hh2
-rw-r--r--cpu/o3/store_set.hh2
-rw-r--r--cpu/o3/tournament_pred.hh2
26 files changed, 221 insertions, 223 deletions
diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index a97ce455c..97433e542 100644
--- a/cpu/o3/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -30,7 +30,7 @@
#define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
class DefaultBP
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 1e1a72af0..b35bcf9e3 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -39,8 +39,9 @@
template <class Impl>
class AlphaFullCPU : public FullO3CPU<Impl>
{
+ protected:
+ typedef TheISA::IntReg IntReg;
public:
- typedef typename Impl::ISA AlphaISA;
typedef typename Impl::Params Params;
public:
@@ -87,7 +88,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// put the asid in the upper 16 bits of the paddr
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
- return No_Fault;
+ return NoFault;
}
Fault translateInstReq(MemReqPtr &req)
@@ -259,7 +260,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
<< "on cpu " << this->cpu_id
<< std::endl;
}
- return No_Fault;
+ return NoFault;
}
else req->xc->storeCondFailures = 0;
}
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 3b16975a9..7ec1ba663 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -280,9 +280,9 @@ AlphaFullCPU<Impl>::hwrei()
uint64_t *ipr = getIpr();
if (!inPalMode())
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
- setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+ this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
// kernelStats.hwrei();
@@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::hwrei()
this->checkInterrupts = true;
// FIXME: XXX check for interrupts? XXX
- return No_Fault;
+ return NoFault;
}
template <class Impl>
@@ -329,22 +329,22 @@ AlphaFullCPU<Impl>::trap(Fault fault)
// miss
uint64_t PC = this->commit.readCommitPC();
- DPRINTF(Fault, "Fault %s\n", FaultName(fault));
- this->recordEvent(csprintf("Fault %s", FaultName(fault)));
+ DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
+ this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
// kernelStats.fault(fault);
- if (fault == Arithmetic_Fault)
+ if (fault == ArithmeticFault)
panic("Arithmetic traps are unimplemented!");
- typename AlphaISA::InternalProcReg *ipr = getIpr();
+ AlphaISA::InternalProcReg *ipr = getIpr();
// exception restart address - Get the commit PC
- if (fault != Interrupt_Fault || !inPalMode(PC))
+ if (fault != InterruptFault || !inPalMode(PC))
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
- if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
- fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
+ if (fault == PalFault || fault == ArithmeticFault /* ||
+ fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
}
@@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
swapPALShadow(true);
this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
- AlphaISA::fault_addr[fault] );
+ AlphaISA::fault_addr(fault) );
this->regFile.setNextPC(PC + sizeof(MachInst));
}
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index bb90bf21a..f282c287c 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -48,21 +48,16 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Typedef for the CPU. */
typedef typename Impl::FullCPU FullCPU;
- /** Typedef to get the ISA. */
- typedef typename Impl::ISA ISA;
-
/** Binary machine instruction type. */
- typedef typename ISA::MachInst MachInst;
- /** Memory address type. */
- typedef typename ISA::Addr Addr;
+ typedef TheISA::MachInst MachInst;
/** Logical register index type. */
- typedef typename ISA::RegIndex RegIndex;
+ typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */
- typedef typename ISA::IntReg IntReg;
+ typedef TheISA::IntReg IntReg;
enum {
- MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
public:
@@ -71,7 +66,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
FullCPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
- AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
+ AlphaDynInst(StaticInstPtr &_staticInst);
/** Executes the instruction.*/
Fault execute()
@@ -130,22 +125,22 @@ class AlphaDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst<ISA> *si, int idx)
+ uint64_t readIntReg(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
- float readFloatRegSingle(const StaticInst<ISA> *si, int idx)
+ float readFloatRegSingle(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
}
- double readFloatRegDouble(const StaticInst<ISA> *si, int idx)
+ double readFloatRegDouble(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
}
- uint64_t readFloatRegInt(const StaticInst<ISA> *si, int idx)
+ uint64_t readFloatRegInt(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
}
@@ -153,25 +148,25 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst<ISA> *si, int idx, uint64_t val)
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
this->instResult.integer = val;
}
- void setFloatRegSingle(const StaticInst<ISA> *si, int idx, float val)
+ void setFloatRegSingle(const StaticInst *si, int idx, float val)
{
this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
this->instResult.fp = val;
}
- void setFloatRegDouble(const StaticInst<ISA> *si, int idx, double val)
+ void setFloatRegDouble(const StaticInst *si, int idx, double val)
{
this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
this->instResult.dbl = val;
}
- void setFloatRegInt(const StaticInst<ISA> *si, int idx, uint64_t val)
+ void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setFloatRegInt(_destRegIdx[idx], val);
this->instResult.integer = val;
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index d1ebb812d..eebe7675a 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -50,7 +50,7 @@ AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
}
template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
+AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
: BaseDynInst<Impl>(_staticInst)
{
// Make sure to have the renamed register entries set to the same
diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh
index 6c1156041..5e39fcb37 100644
--- a/cpu/o3/alpha_impl.hh
+++ b/cpu/o3/alpha_impl.hh
@@ -51,11 +51,8 @@ class AlphaFullCPU;
*/
struct AlphaSimpleImpl
{
- /** The ISA to be used. */
- typedef AlphaISA ISA;
-
/** The type of MachInst. */
- typedef ISA::MachInst MachInst;
+ typedef TheISA::MachInst MachInst;
/** The CPU policy to be used (ie fetch, decode, etc.). */
typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh
index 9cb2e0490..8d16a0cdf 100644
--- a/cpu/o3/bpred_unit_impl.hh
+++ b/cpu/o3/bpred_unit_impl.hh
@@ -98,6 +98,8 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
// Save off record of branch stuff so the RAS can be fixed
// up once it's done.
+ using TheISA::MachInst;
+
bool pred_taken = false;
Addr target;
diff --git a/cpu/o3/btb.cc b/cpu/o3/btb.cc
index 7671e61e2..2d39c3856 100644
--- a/cpu/o3/btb.cc
+++ b/cpu/o3/btb.cc
@@ -30,6 +30,8 @@
#include "base/trace.hh"
#include "cpu/o3/btb.hh"
+using namespace TheISA;
+
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
unsigned _instShiftAmt)
diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh
index a4ddfecb4..77bdc32ea 100644
--- a/cpu/o3/btb.hh
+++ b/cpu/o3/btb.hh
@@ -30,7 +30,7 @@
#define __CPU_O3_CPU_BTB_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
class DefaultBTB
{
diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh
index 6ddc8d6b9..580c1a316 100644
--- a/cpu/o3/commit.hh
+++ b/cpu/o3/commit.hh
@@ -52,7 +52,6 @@ class SimpleCommit
{
public:
// Typedefs from the Impl.
- typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index dc0986772..e289bc0c0 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -395,7 +395,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
- if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
+ if (inst_fault != NoFault) {
if (!head_inst->isNop()) {
#if FULL_SYSTEM
cpu->trap(inst_fault);
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index 6ea0ed7c7..706657887 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -84,14 +84,14 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
- freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
- Impl::ISA::NumFloatRegs, params.numPhysFloatRegs),
+ freeList(TheISA::NumIntRegs, params.numPhysIntRegs,
+ TheISA::NumFloatRegs, params.numPhysFloatRegs),
- renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
- Impl::ISA::NumFloatRegs, params.numPhysFloatRegs,
- Impl::ISA::NumMiscRegs,
- Impl::ISA::ZeroReg,
- Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs),
+ renameMap(TheISA::NumIntRegs, params.numPhysIntRegs,
+ TheISA::NumFloatRegs, params.numPhysFloatRegs,
+ TheISA::NumMiscRegs,
+ TheISA::ZeroReg,
+ TheISA::ZeroReg + TheISA::NumIntRegs),
rob(params.numROBEntries, params.squashWidth),
@@ -253,13 +253,13 @@ FullO3CPU<Impl>::init()
ExecContext *src_xc = thread[0];
#endif
// First loop through the integer registers.
- for (int i = 0; i < Impl::ISA::NumIntRegs; ++i)
+ for (int i = 0; i < TheISA::NumIntRegs; ++i)
{
regFile.intRegFile[i] = src_xc->regs.intRegFile[i];
}
// Then loop through the floating point registers.
- for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i)
+ for (int i = 0; i < TheISA::NumFloatRegs; ++i)
{
regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 75dca5056..321d61dce 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -78,7 +78,6 @@ class FullO3CPU : public BaseFullCPU
{
public:
//Put typedefs from the Impl here.
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -153,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
/** Get instruction asid. */
int getInstAsid()
- { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
+ { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
/** Get data asid. */
int getDataAsid()
- { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
+ { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
#else
bool validInstAddr(Addr addr)
{ return thread[0]->validInstAddr(addr); }
diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh
index 42313d83a..5b9a0f822 100644
--- a/cpu/o3/decode.hh
+++ b/cpu/o3/decode.hh
@@ -39,7 +39,6 @@ class SimpleDecode
{
private:
// Typedefs from the Impl.
- typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
@@ -50,9 +49,6 @@ class SimpleDecode
typedef typename CPUPol::DecodeStruct DecodeStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
- // Typedefs from the ISA.
- typedef typename ISA::Addr Addr;
-
public:
// The only time decode will become blocked is if dispatch becomes
// blocked, which means IQ or ROB is probably full.
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 24e445f0b..cc64800d9 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -49,7 +49,6 @@ class SimpleFetch
{
public:
/** Typedefs from Impl. */
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInst DynInst;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -61,7 +60,7 @@ class SimpleFetch
typedef typename CPUPol::TimeStruct TimeStruct;
/** Typedefs from ISA. */
- typedef typename ISA::MachInst MachInst;
+ typedef TheISA::MachInst MachInst;
public:
enum Status {
@@ -141,7 +140,7 @@ class SimpleFetch
// We fold in the PISA 64- to 32-bit conversion here as well.
Addr icacheBlockAlignPC(Addr addr)
{
- addr = ISA::realPCToFetchPC(addr);
+ addr = TheISA::realPCToFetchPC(addr);
return (addr & ~(cacheBlkMask));
}
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index cd1ed1351..8029fc732 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
unsigned flags = 0;
#endif // FULL_SYSTEM
- Fault fault = No_Fault;
+ Fault fault = NoFault;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
@@ -258,7 +258,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
// If translation was successful, attempt to read the first
// instruction.
- if (fault == No_Fault) {
+ if (fault == NoFault) {
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
fault = cpu->mem->read(memReq, cacheData);
// This read may change when the mem interface changes.
@@ -268,7 +268,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
// Now do the timing access to see whether or not the instruction
// exists within the cache.
- if (icacheInterface && fault == No_Fault) {
+ if (icacheInterface && fault == NoFault) {
DPRINTF(Fetch, "Fetch: Doing timing memory access.\n");
memReq->completionEvent = NULL;
@@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
Addr fetch_PC = cpu->readPC();
// Fault code for memory access.
- Fault fault = No_Fault;
+ Fault fault = NoFault;
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up
@@ -506,7 +506,7 @@ SimpleFetch<Impl>::fetch()
unsigned offset = fetch_PC & cacheBlkMask;
unsigned fetched;
- if (fault == No_Fault) {
+ if (fault == NoFault) {
// If the read of the first instruction was successful, then grab the
// instructions from the rest of the cache line and put them into the
// queue heading to decode.
@@ -582,7 +582,7 @@ SimpleFetch<Impl>::fetch()
// Or might want to leave setting the PC to the main CPU, with fetch
// only changing the nextPC (will require correct determination of
// next PC).
- if (fault == No_Fault) {
+ if (fault == NoFault) {
DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC);
cpu->setPC(next_PC);
cpu->setNextPC(next_PC + instSize);
diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh
index 733d142fc..0b85dba1e 100644
--- a/cpu/o3/free_list.hh
+++ b/cpu/o3/free_list.hh
@@ -32,7 +32,7 @@
#include <iostream>
#include <queue>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/comm.hh"
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index af23c6f45..1e370d4e6 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -45,7 +45,6 @@ class SimpleIEW
{
private:
//Typedefs from Impl
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index b8a2b4dc9..85217dd10 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -256,7 +256,7 @@ SimpleIEW<Impl>::squashDueToBranch(DynInstPtr &inst)
toCommit->branchMispredict = true;
// Prediction was incorrect, so send back inverse.
toCommit->branchTaken = inst->readNextPC() !=
- (inst->readPC() + sizeof(MachInst));
+ (inst->readPC() + sizeof(TheISA::MachInst));
}
template<class Impl>
diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh
index bbc4162a6..46d98181e 100644
--- a/cpu/o3/ras.hh
+++ b/cpu/o3/ras.hh
@@ -30,7 +30,7 @@
#define __CPU_O3_CPU_RAS_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
class ReturnAddrStack
{
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 4d47b8f9c..ee7b8858e 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -32,6 +32,7 @@
// @todo: Destructor
#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/faults.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
@@ -51,6 +52,10 @@ using namespace EV5;
template <class Impl>
class PhysRegFile
{
+ protected:
+ typedef TheISA::IntReg IntReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::MiscRegFile MiscRegFile;
//Note that most of the definitions of the IntReg, FloatReg, etc. exist
//within the Impl/ISA class and not within this PhysRegFile class.
@@ -61,7 +66,6 @@ class PhysRegFile
//Will make these registers public for now, but they probably should
//be private eventually with some accessor functions.
public:
- typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
PhysRegFile(unsigned _numPhysicalIntRegs,
@@ -280,73 +284,73 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
uint64_t retval = 0; // return value, default 0
switch (idx) {
- case ISA::IPR_PALtemp0:
- case ISA::IPR_PALtemp1:
- case ISA::IPR_PALtemp2:
- case ISA::IPR_PALtemp3:
- case ISA::IPR_PALtemp4:
- case ISA::IPR_PALtemp5:
- case ISA::IPR_PALtemp6:
- case ISA::IPR_PALtemp7:
- case ISA::IPR_PALtemp8:
- case ISA::IPR_PALtemp9:
- case ISA::IPR_PALtemp10:
- case ISA::IPR_PALtemp11:
- case ISA::IPR_PALtemp12:
- case ISA::IPR_PALtemp13:
- case ISA::IPR_PALtemp14:
- case ISA::IPR_PALtemp15:
- case ISA::IPR_PALtemp16:
- case ISA::IPR_PALtemp17:
- case ISA::IPR_PALtemp18:
- case ISA::IPR_PALtemp19:
- case ISA::IPR_PALtemp20:
- case ISA::IPR_PALtemp21:
- case ISA::IPR_PALtemp22:
- case ISA::IPR_PALtemp23:
- case ISA::IPR_PAL_BASE:
-
- case ISA::IPR_IVPTBR:
- case ISA::IPR_DC_MODE:
- case ISA::IPR_MAF_MODE:
- case ISA::IPR_ISR:
- case ISA::IPR_EXC_ADDR:
- case ISA::IPR_IC_PERR_STAT:
- case ISA::IPR_DC_PERR_STAT:
- case ISA::IPR_MCSR:
- case ISA::IPR_ASTRR:
- case ISA::IPR_ASTER:
- case ISA::IPR_SIRR:
- case ISA::IPR_ICSR:
- case ISA::IPR_ICM:
- case ISA::IPR_DTB_CM:
- case ISA::IPR_IPLR:
- case ISA::IPR_INTID:
- case ISA::IPR_PMCTR:
+ case TheISA::IPR_PALtemp0:
+ case TheISA::IPR_PALtemp1:
+ case TheISA::IPR_PALtemp2:
+ case TheISA::IPR_PALtemp3:
+ case TheISA::IPR_PALtemp4:
+ case TheISA::IPR_PALtemp5:
+ case TheISA::IPR_PALtemp6:
+ case TheISA::IPR_PALtemp7:
+ case TheISA::IPR_PALtemp8:
+ case TheISA::IPR_PALtemp9:
+ case TheISA::IPR_PALtemp10:
+ case TheISA::IPR_PALtemp11:
+ case TheISA::IPR_PALtemp12:
+ case TheISA::IPR_PALtemp13:
+ case TheISA::IPR_PALtemp14:
+ case TheISA::IPR_PALtemp15:
+ case TheISA::IPR_PALtemp16:
+ case TheISA::IPR_PALtemp17:
+ case TheISA::IPR_PALtemp18:
+ case TheISA::IPR_PALtemp19:
+ case TheISA::IPR_PALtemp20:
+ case TheISA::IPR_PALtemp21:
+ case TheISA::IPR_PALtemp22:
+ case TheISA::IPR_PALtemp23:
+ case TheISA::IPR_PAL_BASE:
+
+ case TheISA::IPR_IVPTBR:
+ case TheISA::IPR_DC_MODE:
+ case TheISA::IPR_MAF_MODE:
+ case TheISA::IPR_ISR:
+ case TheISA::IPR_EXC_ADDR:
+ case TheISA::IPR_IC_PERR_STAT:
+ case TheISA::IPR_DC_PERR_STAT:
+ case TheISA::IPR_MCSR:
+ case TheISA::IPR_ASTRR:
+ case TheISA::IPR_ASTER:
+ case TheISA::IPR_SIRR:
+ case TheISA::IPR_ICSR:
+ case TheISA::IPR_ICM:
+ case TheISA::IPR_DTB_CM:
+ case TheISA::IPR_IPLR:
+ case TheISA::IPR_INTID:
+ case TheISA::IPR_PMCTR:
// no side-effect
retval = ipr[idx];
break;
- case ISA::IPR_CC:
+ case TheISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
retval |= curTick & ULL(0x00000000ffffffff);
break;
- case ISA::IPR_VA:
+ case TheISA::IPR_VA:
retval = ipr[idx];
break;
- case ISA::IPR_VA_FORM:
- case ISA::IPR_MM_STAT:
- case ISA::IPR_IFAULT_VA_FORM:
- case ISA::IPR_EXC_MASK:
- case ISA::IPR_EXC_SUM:
+ case TheISA::IPR_VA_FORM:
+ case TheISA::IPR_MM_STAT:
+ case TheISA::IPR_IFAULT_VA_FORM:
+ case TheISA::IPR_EXC_MASK:
+ case TheISA::IPR_EXC_SUM:
retval = ipr[idx];
break;
- case ISA::IPR_DTB_PTE:
+ case TheISA::IPR_DTB_PTE:
{
- typename ISA::PTE &pte = cpu->dtb->index(1);
+ TheISA::PTE &pte = cpu->dtb->index(1);
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -359,21 +363,21 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
break;
// write only registers
- case ISA::IPR_HWINT_CLR:
- case ISA::IPR_SL_XMIT:
- case ISA::IPR_DC_FLUSH:
- case ISA::IPR_IC_FLUSH:
- case ISA::IPR_ALT_MODE:
- case ISA::IPR_DTB_IA:
- case ISA::IPR_DTB_IAP:
- case ISA::IPR_ITB_IA:
- case ISA::IPR_ITB_IAP:
- fault = Unimplemented_Opcode_Fault;
+ case TheISA::IPR_HWINT_CLR:
+ case TheISA::IPR_SL_XMIT:
+ case TheISA::IPR_DC_FLUSH:
+ case TheISA::IPR_IC_FLUSH:
+ case TheISA::IPR_ALT_MODE:
+ case TheISA::IPR_DTB_IA:
+ case TheISA::IPR_DTB_IAP:
+ case TheISA::IPR_ITB_IA:
+ case TheISA::IPR_ITB_IAP:
+ fault = UnimplementedOpcodeFault;
break;
default:
// invalid IPR
- fault = Unimplemented_Opcode_Fault;
+ fault = UnimplementedOpcodeFault;
break;
}
@@ -389,195 +393,195 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
uint64_t old;
switch (idx) {
- case ISA::IPR_PALtemp0:
- case ISA::IPR_PALtemp1:
- case ISA::IPR_PALtemp2:
- case ISA::IPR_PALtemp3:
- case ISA::IPR_PALtemp4:
- case ISA::IPR_PALtemp5:
- case ISA::IPR_PALtemp6:
- case ISA::IPR_PALtemp7:
- case ISA::IPR_PALtemp8:
- case ISA::IPR_PALtemp9:
- case ISA::IPR_PALtemp10:
- case ISA::IPR_PALtemp11:
- case ISA::IPR_PALtemp12:
- case ISA::IPR_PALtemp13:
- case ISA::IPR_PALtemp14:
- case ISA::IPR_PALtemp15:
- case ISA::IPR_PALtemp16:
- case ISA::IPR_PALtemp17:
- case ISA::IPR_PALtemp18:
- case ISA::IPR_PALtemp19:
- case ISA::IPR_PALtemp20:
- case ISA::IPR_PALtemp21:
- case ISA::IPR_PALtemp22:
- case ISA::IPR_PAL_BASE:
- case ISA::IPR_IC_PERR_STAT:
- case ISA::IPR_DC_PERR_STAT:
- case ISA::IPR_PMCTR:
+ case TheISA::IPR_PALtemp0:
+ case TheISA::IPR_PALtemp1:
+ case TheISA::IPR_PALtemp2:
+ case TheISA::IPR_PALtemp3:
+ case TheISA::IPR_PALtemp4:
+ case TheISA::IPR_PALtemp5:
+ case TheISA::IPR_PALtemp6:
+ case TheISA::IPR_PALtemp7:
+ case TheISA::IPR_PALtemp8:
+ case TheISA::IPR_PALtemp9:
+ case TheISA::IPR_PALtemp10:
+ case TheISA::IPR_PALtemp11:
+ case TheISA::IPR_PALtemp12:
+ case TheISA::IPR_PALtemp13:
+ case TheISA::IPR_PALtemp14:
+ case TheISA::IPR_PALtemp15:
+ case TheISA::IPR_PALtemp16:
+ case TheISA::IPR_PALtemp17:
+ case TheISA::IPR_PALtemp18:
+ case TheISA::IPR_PALtemp19:
+ case TheISA::IPR_PALtemp20:
+ case TheISA::IPR_PALtemp21:
+ case TheISA::IPR_PALtemp22:
+ case TheISA::IPR_PAL_BASE:
+ case TheISA::IPR_IC_PERR_STAT:
+ case TheISA::IPR_DC_PERR_STAT:
+ case TheISA::IPR_PMCTR:
// write entire quad w/ no side-effect
ipr[idx] = val;
break;
- case ISA::IPR_CC_CTL:
+ case TheISA::IPR_CC_CTL:
// This IPR resets the cycle counter. We assume this only
// happens once... let's verify that.
assert(ipr[idx] == 0);
ipr[idx] = 1;
break;
- case ISA::IPR_CC:
+ case TheISA::IPR_CC:
// This IPR only writes the upper 64 bits. It's ok to write
// all 64 here since we mask out the lower 32 in rpcc (see
// isa_desc).
ipr[idx] = val;
break;
- case ISA::IPR_PALtemp23:
+ case TheISA::IPR_PALtemp23:
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
break;
- case ISA::IPR_DTB_PTE:
+ case TheISA::IPR_DTB_PTE:
// write entire quad w/ no side-effect, tag is forthcoming
ipr[idx] = val;
break;
- case ISA::IPR_EXC_ADDR:
+ case TheISA::IPR_EXC_ADDR:
// second least significant bit in PC is always zero
ipr[idx] = val & ~2;
break;
- case ISA::IPR_ASTRR:
- case ISA::IPR_ASTER:
+ case TheISA::IPR_ASTRR:
+ case TheISA::IPR_ASTER:
// only write least significant four bits - privilege mask
ipr[idx] = val & 0xf;
break;
- case ISA::IPR_IPLR:
+ case TheISA::IPR_IPLR:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
break;
- case ISA::IPR_DTB_CM:
+ case TheISA::IPR_DTB_CM:
- case ISA::IPR_ICM:
+ case TheISA::IPR_ICM:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
- case ISA::IPR_ALT_MODE:
+ case TheISA::IPR_ALT_MODE:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
- case ISA::IPR_MCSR:
+ case TheISA::IPR_MCSR:
// more here after optimization...
ipr[idx] = val;
break;
- case ISA::IPR_SIRR:
+ case TheISA::IPR_SIRR:
// only write software interrupt mask
ipr[idx] = val & 0x7fff0;
break;
- case ISA::IPR_ICSR:
+ case TheISA::IPR_ICSR:
ipr[idx] = val & ULL(0xffffff0300);
break;
- case ISA::IPR_IVPTBR:
- case ISA::IPR_MVPTBR:
+ case TheISA::IPR_IVPTBR:
+ case TheISA::IPR_MVPTBR:
ipr[idx] = val & ULL(0xffffffffc0000000);
break;
- case ISA::IPR_DC_TEST_CTL:
+ case TheISA::IPR_DC_TEST_CTL:
ipr[idx] = val & 0x1ffb;
break;
- case ISA::IPR_DC_MODE:
- case ISA::IPR_MAF_MODE:
+ case TheISA::IPR_DC_MODE:
+ case TheISA::IPR_MAF_MODE:
ipr[idx] = val & 0x3f;
break;
- case ISA::IPR_ITB_ASN:
+ case TheISA::IPR_ITB_ASN:
ipr[idx] = val & 0x7f0;
break;
- case ISA::IPR_DTB_ASN:
+ case TheISA::IPR_DTB_ASN:
ipr[idx] = val & ULL(0xfe00000000000000);
break;
- case ISA::IPR_EXC_SUM:
- case ISA::IPR_EXC_MASK:
+ case TheISA::IPR_EXC_SUM:
+ case TheISA::IPR_EXC_MASK:
// any write to this register clears it
ipr[idx] = 0;
break;
- case ISA::IPR_INTID:
- case ISA::IPR_SL_RCV:
- case ISA::IPR_MM_STAT:
- case ISA::IPR_ITB_PTE_TEMP:
- case ISA::IPR_DTB_PTE_TEMP:
+ case TheISA::IPR_INTID:
+ case TheISA::IPR_SL_RCV:
+ case TheISA::IPR_MM_STAT:
+ case TheISA::IPR_ITB_PTE_TEMP:
+ case TheISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
- case ISA::IPR_HWINT_CLR:
- case ISA::IPR_SL_XMIT:
- case ISA::IPR_DC_FLUSH:
- case ISA::IPR_IC_FLUSH:
+ case TheISA::IPR_HWINT_CLR:
+ case TheISA::IPR_SL_XMIT:
+ case TheISA::IPR_DC_FLUSH:
+ case TheISA::IPR_IC_FLUSH:
// the following are write only
ipr[idx] = val;
break;
- case ISA::IPR_DTB_IA:
+ case TheISA::IPR_DTB_IA:
// really a control write
ipr[idx] = 0;
cpu->dtb->flushAll();
break;
- case ISA::IPR_DTB_IAP:
+ case TheISA::IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
cpu->dtb->flushProcesses();
break;
- case ISA::IPR_DTB_IS:
+ case TheISA::IPR_DTB_IS:
// really a control write
ipr[idx] = val;
- cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
+ cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
break;
- case ISA::IPR_DTB_TAG: {
- struct ISA::PTE pte;
+ case TheISA::IPR_DTB_TAG: {
+ struct TheISA::PTE pte;
// FIXME: granularity hints NYI...
- if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
+ if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
- pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
- pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
- pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
- pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
- pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
- pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
+ pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
+ pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
+ pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
+ pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
+ pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
+ pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
+ pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
cpu->dtb->insert(val, pte);
}
break;
- case ISA::IPR_ITB_PTE: {
- struct ISA::PTE pte;
+ case TheISA::IPR_ITB_PTE: {
+ struct TheISA::PTE pte;
// FIXME: granularity hints NYI...
if (ITB_PTE_GH(val) != 0)
@@ -593,41 +597,41 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
pte.fonr = ITB_PTE_FONR(val);
pte.fonw = ITB_PTE_FONW(val);
pte.asma = ITB_PTE_ASMA(val);
- pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
+ pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
- cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
+ cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
}
break;
- case ISA::IPR_ITB_IA:
+ case TheISA::IPR_ITB_IA:
// really a control write
ipr[idx] = 0;
cpu->itb->flushAll();
break;
- case ISA::IPR_ITB_IAP:
+ case TheISA::IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
cpu->itb->flushProcesses();
break;
- case ISA::IPR_ITB_IS:
+ case TheISA::IPR_ITB_IS:
// really a control write
ipr[idx] = val;
- cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
+ cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
break;
default:
// invalid IPR
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
}
// no error...
- return No_Fault;
+ return NoFault;
}
#endif // #if FULL_SYSTEM
diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh
index a17ec7311..07b442964 100644
--- a/cpu/o3/rename.hh
+++ b/cpu/o3/rename.hh
@@ -46,7 +46,6 @@ class SimpleRename
{
public:
// Typedefs from the Impl.
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU;
@@ -62,7 +61,7 @@ class SimpleRename
typedef typename CPUPol::RenameMap RenameMap;
// Typedefs from the ISA.
- typedef typename ISA::Addr Addr;
+ typedef TheISA::RegIndex RegIndex;
public:
// Rename will block if ROB becomes full or issue queue becomes full,
diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh
index c44c7a1ea..57be4a64a 100644
--- a/cpu/o3/rename_map.hh
+++ b/cpu/o3/rename_map.hh
@@ -38,9 +38,13 @@
#include <vector>
#include "cpu/o3/free_list.hh"
+//For RegIndex
+#include "arch/isa_traits.hh"
class SimpleRenameMap
{
+ protected:
+ typedef TheISA::RegIndex RegIndex;
public:
/**
* Pair of a logical register and a physical register. Tells the
diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh
index 29ec48007..1185564ad 100644
--- a/cpu/o3/rob.hh
+++ b/cpu/o3/rob.hh
@@ -47,6 +47,8 @@
template <class Impl>
class ROB
{
+ protected:
+ typedef TheISA::RegIndex RegIndex;
public:
//Typedefs from the Impl.
typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh
index bcd590384..5a885d838 100644
--- a/cpu/o3/store_set.hh
+++ b/cpu/o3/store_set.hh
@@ -31,7 +31,7 @@
#include <vector>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
class StoreSet
diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index 58ea1a7d9..cb93c2f67 100644
--- a/cpu/o3/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -30,7 +30,7 @@
#define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
class TournamentBP
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 10:28:47 +0000