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-rw-r--r--cpu/o3/alpha_cpu.hh4
-rw-r--r--cpu/o3/alpha_cpu_impl.hh3
-rw-r--r--cpu/o3/fetch_impl.hh4
3 files changed, 4 insertions, 7 deletions
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index cba57d189..164da4968 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -220,7 +220,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
Fault error;
error = this->mem->read(req, data);
- data = gtoh(data);
+ data = LittleEndianGuest::gtoh(data);
return error;
}
@@ -277,7 +277,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
#endif
- return this->mem->write(req, (T)htog(data));
+ return this->mem->write(req, (T)LittleEndianGuest::htog(data));
}
template <class T>
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 2a764740b..3b16975a9 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -42,9 +42,6 @@
#if FULL_SYSTEM
#include "arch/alpha/osfpal.hh"
#include "arch/alpha/isa_traits.hh"
-//#include "arch/alpha/ev5.hh"
-
-//using namespace EV5;
#endif
template <class Impl>
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index c943fd36a..1a8411cc1 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -30,7 +30,7 @@
#define OPCODE(X) (X >> 26) & 0x3f
-#include "arch/alpha/byte_swap.hh"
+#include "sim/byteswap.hh"
#include "cpu/exetrace.hh"
#include "mem/base_mem.hh"
#include "mem/mem_interface.hh"
@@ -535,7 +535,7 @@ SimpleFetch<Impl>::fetch()
assert(offset <= cacheBlkSize - instSize);
// Get the instruction from the array of the cache line.
- inst = gtoh(*reinterpret_cast<MachInst *>
+ inst = LittleEndianGuest::gtoh(*reinterpret_cast<MachInst *>
(&cacheData[offset]));
// Create a new DynInst from the instruction fetched.