diff options
Diffstat (limited to 'cpu/o3')
| -rw-r--r-- | cpu/o3/alpha_cpu.hh | 50 | ||||
| -rw-r--r-- | cpu/o3/alpha_cpu_impl.hh | 46 | ||||
| -rw-r--r-- | cpu/o3/alpha_dyn_inst.hh | 34 | ||||
| -rw-r--r-- | cpu/o3/alpha_dyn_inst_impl.hh | 42 | ||||
| -rw-r--r-- | cpu/o3/cpu.cc | 4 | ||||
| -rw-r--r-- | cpu/o3/cpu.hh | 4 | ||||
| -rw-r--r-- | cpu/o3/regfile.hh | 391 |
7 files changed, 77 insertions, 494 deletions
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index ea0aae41f..38c00a3a9 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -41,6 +41,8 @@ class AlphaFullCPU : public FullO3CPU<Impl> { protected: typedef TheISA::IntReg IntReg; + typedef TheISA::MiscReg MiscReg; + public: typedef typename Impl::Params Params; @@ -111,33 +113,24 @@ class AlphaFullCPU : public FullO3CPU<Impl> // Later on may want to remove this misc stuff from the regfile and // have it handled at this level. Might prove to be an issue when // trying to rename source/destination registers... - uint64_t readUniq() - { - return this->regFile.readUniq(); - } - - void setUniq(uint64_t val) + MiscReg readMiscReg(int misc_reg) { - this->regFile.setUniq(val); + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; } - uint64_t readFpcr() + Fault setMiscReg(int misc_reg, const MiscReg &val) { - return this->regFile.readFpcr(); - } - - void setFpcr(uint64_t val) - { - this->regFile.setFpcr(val); + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; } // Most of the full system code and syscall emulation is not yet // implemented. These functions do show what the final interface will // look like. #if FULL_SYSTEM - uint64_t *getIpr(); - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); int readIntrFlag(); void setIntrFlag(int val); Fault hwrei(); @@ -216,8 +209,8 @@ class AlphaFullCPU : public FullO3CPU<Impl> #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { MiscRegFile *cregs = &req->xc->regs.miscRegs; - cregs->lock_addr = req->paddr; - cregs->lock_flag = true; + cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr); + cregs->setReg(TheISA::Lock_Flag_DepTag, true); } #endif @@ -242,22 +235,24 @@ class AlphaFullCPU : public FullO3CPU<Impl> // If this is a store conditional, act appropriately if (req->flags & LOCKED) { - cregs = &this->xc->regs.miscRegs; + cregs = &req->xc->regs.miscRegs; if (req->flags & UNCACHEABLE) { // Don't update result register (see stq_c in isa_desc) req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { - req->result = cregs->lock_flag; - if (!cregs->lock_flag || - ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { - cregs->lock_flag = false; + bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag); + Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag); + req->result = lock_flag; + if (!lock_flag || + ((lock_addr & ~0xf) != (req->paddr & ~0xf))) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); if (((++req->xc->storeCondFailures) % 100000) == 0) { std::cerr << "Warning: " << req->xc->storeCondFailures << " consecutive store conditional failures " - << "on cpu " << this->cpu_id + << "on cpu " << req->xc->cpu_id << std::endl; } return NoFault; @@ -273,8 +268,9 @@ class AlphaFullCPU : public FullO3CPU<Impl> // through. for (int i = 0; i < this->system->execContexts.size(); i++){ cregs = &this->system->execContexts[i]->regs.miscRegs; - if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { - cregs->lock_flag = false; + if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) == + (req->paddr & ~0xf)) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); } } diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 9b7cd8a0e..daa61bb1c 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -179,12 +179,12 @@ AlphaFullCPU<Impl>::copyToXC() this->xc->regs.floatRegFile.q[i] = this->regFile.readFloatRegInt(renamed_reg); } - +/* this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr; this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq; this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag; this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr; - +*/ this->xc->regs.pc = this->rob.readHeadPC(); this->xc->regs.npc = this->xc->regs.pc+4; @@ -221,13 +221,13 @@ AlphaFullCPU<Impl>::copyFromXC() this->regFile.setFloatRegInt(renamed_reg, this->xc->regs.floatRegFile.q[i]); } - + /* // Then loop through the misc registers. this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr; this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq; this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag; this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr; - + */ // Then finally set the PC and the next PC. // regFile.pc = xc->regs.pc; // regFile.npc = xc->regs.npc; @@ -238,27 +238,6 @@ AlphaFullCPU<Impl>::copyFromXC() #if FULL_SYSTEM template <class Impl> -uint64_t * -AlphaFullCPU<Impl>::getIpr() -{ - return this->regFile.getIpr(); -} - -template <class Impl> -uint64_t -AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault) -{ - return this->regFile.readIpr(idx, fault); -} - -template <class Impl> -Fault -AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val) -{ - return this->regFile.setIpr(idx, val); -} - -template <class Impl> int AlphaFullCPU<Impl>::readIntrFlag() { @@ -277,16 +256,14 @@ template <class Impl> Fault AlphaFullCPU<Impl>::hwrei() { - uint64_t *ipr = getIpr(); - if (!inPalMode()) return new UnimplementedOpcodeFault; - this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); + this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR)); // kernelStats.hwrei(); - if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) + if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0) // AlphaISA::swap_palshadow(®s, false); this->checkInterrupts = true; @@ -337,22 +314,23 @@ AlphaFullCPU<Impl>::trap(Fault fault) if (fault->isA<ArithmeticFault>()) panic("Arithmetic traps are unimplemented!"); - AlphaISA::InternalProcReg *ipr = getIpr(); - // exception restart address - Get the commit PC if (!fault->isA<InterruptFault>() || !inPalMode(PC)) - ipr[AlphaISA::IPR_EXC_ADDR] = PC; + this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC); if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* || fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction - ipr[AlphaISA::IPR_EXC_ADDR] += 4; + AlphaISA::MiscReg ipr_exc_addr = + this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR); + this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, + ipr_exc_addr + 4); } if (!inPalMode(PC)) swapPALShadow(true); - this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + + this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) + (dynamic_cast<AlphaFault *>(fault.get()))->vect()); this->regFile.setNextPC(PC + sizeof(MachInst)); } diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index f282c287c..e7f7d3a57 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -54,6 +54,8 @@ class AlphaDynInst : public BaseDynInst<Impl> typedef TheISA::RegIndex RegIndex; /** Integer register index type. */ typedef TheISA::IntReg IntReg; + /** Misc register index type. */ + typedef TheISA::MiscReg MiscReg; enum { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs @@ -75,15 +77,35 @@ class AlphaDynInst : public BaseDynInst<Impl> } public: - uint64_t readUniq(); - void setUniq(uint64_t val); + MiscReg readMiscReg(int misc_reg) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; + } + + MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; + } - uint64_t readFpcr(); - void setFpcr(uint64_t val); + Fault setMiscReg(int misc_reg, const MiscReg &val) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; + } + + Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; + } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); Fault hwrei(); int readIntrFlag(); void setIntrFlag(int val); diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh index eebe7675a..96b7d3430 100644 --- a/cpu/o3/alpha_dyn_inst_impl.hh +++ b/cpu/o3/alpha_dyn_inst_impl.hh @@ -67,50 +67,8 @@ AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst) } } -template <class Impl> -uint64_t -AlphaDynInst<Impl>::readUniq() -{ - return this->cpu->readUniq(); -} - -template <class Impl> -void -AlphaDynInst<Impl>::setUniq(uint64_t val) -{ - this->cpu->setUniq(val); -} - -template <class Impl> -uint64_t -AlphaDynInst<Impl>::readFpcr() -{ - return this->cpu->readFpcr(); -} - -template <class Impl> -void -AlphaDynInst<Impl>::setFpcr(uint64_t val) -{ - this->cpu->setFpcr(val); -} - #if FULL_SYSTEM template <class Impl> -uint64_t -AlphaDynInst<Impl>::readIpr(int idx, Fault &fault) -{ - return this->cpu->readIpr(idx, fault); -} - -template <class Impl> -Fault -AlphaDynInst<Impl>::setIpr(int idx, uint64_t val) -{ - return this->cpu->setIpr(idx, val); -} - -template <class Impl> Fault AlphaDynInst<Impl>::hwrei() { diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 706657887..a8c620028 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -264,13 +264,13 @@ FullO3CPU<Impl>::init() regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i]; regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i]; } - +/* // Then loop through the misc registers. regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr; regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq; regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag; regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr; - +*/ // Then finally set the PC and the next PC. regFile.pc = src_xc->regs.pc; regFile.npc = src_xc->regs.npc; diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 802860ab5..02908887e 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -152,11 +152,11 @@ class FullO3CPU : public BaseFullCPU /** Get instruction asid. */ int getInstAsid() - { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); } + { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); } /** Get data asid. */ int getDataAsid() - { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); } + { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); } #else bool validInstAddr(Addr addr) { return thread[0]->validInstAddr(addr); } diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 3bf96a37b..691a75382 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -56,6 +56,8 @@ class PhysRegFile typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::MiscRegFile MiscRegFile; + typedef TheISA::MiscReg MiscReg; + //Note that most of the definitions of the IntReg, FloatReg, etc. exist //within the Impl/ISA class and not within this PhysRegFile class. @@ -194,30 +196,21 @@ class PhysRegFile //Consider leaving this stuff and below in some implementation specific //file as opposed to the general register file. Or have a derived class. - uint64_t readUniq() - { - return miscRegs.uniq; - } - - void setUniq(uint64_t val) - { - miscRegs.uniq = val; - } - - uint64_t readFpcr() + MiscReg readMiscReg(int misc_reg) { - return miscRegs.fpcr; + // Dummy function for now. + // @todo: Fix this once proxy XC is used. + return 0; } - void setFpcr(uint64_t val) + Fault setMiscReg(int misc_reg, const MiscReg &val) { - miscRegs.fpcr = val; + // Dummy function for now. + // @todo: Fix this once proxy XC is used. + return NoFault; } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); - InternalProcReg *getIpr() { return ipr; } int readIntrFlag() { return intrflag; } void setIntrFlag(int val) { intrflag = val; } #endif @@ -272,368 +265,4 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, memset(floatRegFile, 0, sizeof(*floatRegFile)); } -#if FULL_SYSTEM - -//Problem: This code doesn't make sense at the RegFile level because it -//needs things such as the itb and dtb. Either put it at the CPU level or -//the DynInst level. -template <class Impl> -uint64_t -PhysRegFile<Impl>::readIpr(int idx, Fault &fault) -{ - uint64_t retval = 0; // return value, default 0 - - switch (idx) { - case TheISA::IPR_PALtemp0: - case TheISA::IPR_PALtemp1: - case TheISA::IPR_PALtemp2: - case TheISA::IPR_PALtemp3: - case TheISA::IPR_PALtemp4: - case TheISA::IPR_PALtemp5: - case TheISA::IPR_PALtemp6: - case TheISA::IPR_PALtemp7: - case TheISA::IPR_PALtemp8: - case TheISA::IPR_PALtemp9: - case TheISA::IPR_PALtemp10: - case TheISA::IPR_PALtemp11: - case TheISA::IPR_PALtemp12: - case TheISA::IPR_PALtemp13: - case TheISA::IPR_PALtemp14: - case TheISA::IPR_PALtemp15: - case TheISA::IPR_PALtemp16: - case TheISA::IPR_PALtemp17: - case TheISA::IPR_PALtemp18: - case TheISA::IPR_PALtemp19: - case TheISA::IPR_PALtemp20: - case TheISA::IPR_PALtemp21: - case TheISA::IPR_PALtemp22: - case TheISA::IPR_PALtemp23: - case TheISA::IPR_PAL_BASE: - - case TheISA::IPR_IVPTBR: - case TheISA::IPR_DC_MODE: - case TheISA::IPR_MAF_MODE: - case TheISA::IPR_ISR: - case TheISA::IPR_EXC_ADDR: - case TheISA::IPR_IC_PERR_STAT: - case TheISA::IPR_DC_PERR_STAT: - case TheISA::IPR_MCSR: - case TheISA::IPR_ASTRR: - case TheISA::IPR_ASTER: - case TheISA::IPR_SIRR: - case TheISA::IPR_ICSR: - case TheISA::IPR_ICM: - case TheISA::IPR_DTB_CM: - case TheISA::IPR_IPLR: - case TheISA::IPR_INTID: - case TheISA::IPR_PMCTR: - // no side-effect - retval = ipr[idx]; - break; - - case TheISA::IPR_CC: - retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= curTick & ULL(0x00000000ffffffff); - break; - - case TheISA::IPR_VA: - retval = ipr[idx]; - break; - - case TheISA::IPR_VA_FORM: - case TheISA::IPR_MM_STAT: - case TheISA::IPR_IFAULT_VA_FORM: - case TheISA::IPR_EXC_MASK: - case TheISA::IPR_EXC_SUM: - retval = ipr[idx]; - break; - - case TheISA::IPR_DTB_PTE: - { - TheISA::PTE &pte = cpu->dtb->index(1); - - retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; - retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; - retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; - retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; - retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; - retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; - retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; - } - break; - - // write only registers - case TheISA::IPR_HWINT_CLR: - case TheISA::IPR_SL_XMIT: - case TheISA::IPR_DC_FLUSH: - case TheISA::IPR_IC_FLUSH: - case TheISA::IPR_ALT_MODE: - case TheISA::IPR_DTB_IA: - case TheISA::IPR_DTB_IAP: - case TheISA::IPR_ITB_IA: - case TheISA::IPR_ITB_IAP: - fault = new UnimplementedOpcodeFault; - break; - - default: - // invalid IPR - fault = new UnimplementedOpcodeFault; - break; - } - - return retval; -} - -extern int break_ipl; - -template <class Impl> -Fault -PhysRegFile<Impl>::setIpr(int idx, uint64_t val) -{ - uint64_t old; - - switch (idx) { - case TheISA::IPR_PALtemp0: - case TheISA::IPR_PALtemp1: - case TheISA::IPR_PALtemp2: - case TheISA::IPR_PALtemp3: - case TheISA::IPR_PALtemp4: - case TheISA::IPR_PALtemp5: - case TheISA::IPR_PALtemp6: - case TheISA::IPR_PALtemp7: - case TheISA::IPR_PALtemp8: - case TheISA::IPR_PALtemp9: - case TheISA::IPR_PALtemp10: - case TheISA::IPR_PALtemp11: - case TheISA::IPR_PALtemp12: - case TheISA::IPR_PALtemp13: - case TheISA::IPR_PALtemp14: - case TheISA::IPR_PALtemp15: - case TheISA::IPR_PALtemp16: - case TheISA::IPR_PALtemp17: - case TheISA::IPR_PALtemp18: - case TheISA::IPR_PALtemp19: - case TheISA::IPR_PALtemp20: - case TheISA::IPR_PALtemp21: - case TheISA::IPR_PALtemp22: - case TheISA::IPR_PAL_BASE: - case TheISA::IPR_IC_PERR_STAT: - case TheISA::IPR_DC_PERR_STAT: - case TheISA::IPR_PMCTR: - // write entire quad w/ no side-effect - ipr[idx] = val; - break; - - case TheISA::IPR_CC_CTL: - // This IPR resets the cycle counter. We assume this only - // happens once... let's verify that. - assert(ipr[idx] == 0); - ipr[idx] = 1; - break; - - case TheISA::IPR_CC: - // This IPR only writes the upper 64 bits. It's ok to write - // all 64 here since we mask out the lower 32 in rpcc (see - // isa_desc). - ipr[idx] = val; - break; - - case TheISA::IPR_PALtemp23: - // write entire quad w/ no side-effect - old = ipr[idx]; - ipr[idx] = val; - break; - - case TheISA::IPR_DTB_PTE: - // write entire quad w/ no side-effect, tag is forthcoming - ipr[idx] = val; - break; - - case TheISA::IPR_EXC_ADDR: - // second least significant bit in PC is always zero - ipr[idx] = val & ~2; - break; - - case TheISA::IPR_ASTRR: - case TheISA::IPR_ASTER: - // only write least significant four bits - privilege mask - ipr[idx] = val & 0xf; - break; - - case TheISA::IPR_IPLR: - // only write least significant five bits - interrupt level - ipr[idx] = val & 0x1f; - break; - - case TheISA::IPR_DTB_CM: - - case TheISA::IPR_ICM: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case TheISA::IPR_ALT_MODE: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case TheISA::IPR_MCSR: - // more here after optimization... - ipr[idx] = val; - break; - - case TheISA::IPR_SIRR: - // only write software interrupt mask - ipr[idx] = val & 0x7fff0; - break; - - case TheISA::IPR_ICSR: - ipr[idx] = val & ULL(0xffffff0300); - break; - - case TheISA::IPR_IVPTBR: - case TheISA::IPR_MVPTBR: - ipr[idx] = val & ULL(0xffffffffc0000000); - break; - - case TheISA::IPR_DC_TEST_CTL: - ipr[idx] = val & 0x1ffb; - break; - - case TheISA::IPR_DC_MODE: - case TheISA::IPR_MAF_MODE: - ipr[idx] = val & 0x3f; - break; - - case TheISA::IPR_ITB_ASN: - ipr[idx] = val & 0x7f0; - break; - - case TheISA::IPR_DTB_ASN: - ipr[idx] = val & ULL(0xfe00000000000000); - break; - - case TheISA::IPR_EXC_SUM: - case TheISA::IPR_EXC_MASK: - // any write to this register clears it - ipr[idx] = 0; - break; - - case TheISA::IPR_INTID: - case TheISA::IPR_SL_RCV: - case TheISA::IPR_MM_STAT: - case TheISA::IPR_ITB_PTE_TEMP: - case TheISA::IPR_DTB_PTE_TEMP: - // read-only registers - return new UnimplementedOpcodeFault; - - case TheISA::IPR_HWINT_CLR: - case TheISA::IPR_SL_XMIT: - case TheISA::IPR_DC_FLUSH: - case TheISA::IPR_IC_FLUSH: - // the following are write only - ipr[idx] = val; - break; - - case TheISA::IPR_DTB_IA: - // really a control write - ipr[idx] = 0; - - cpu->dtb->flushAll(); - break; - - case TheISA::IPR_DTB_IAP: - // really a control write - ipr[idx] = 0; - - cpu->dtb->flushProcesses(); - break; - - case TheISA::IPR_DTB_IS: - // really a control write - ipr[idx] = val; - - cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN])); - break; - - case TheISA::IPR_DTB_TAG: { - struct TheISA::PTE pte; - - // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]); - - // insert new TAG/PTE value into data TLB - cpu->dtb->insert(val, pte); - } - break; - - case TheISA::IPR_ITB_PTE: { - struct TheISA::PTE pte; - - // FIXME: granularity hints NYI... - if (ITB_PTE_GH(val) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = ITB_PTE_PPN(val); - pte.xre = ITB_PTE_XRE(val); - pte.xwe = 0; - pte.fonr = ITB_PTE_FONR(val); - pte.fonw = ITB_PTE_FONW(val); - pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]); - - // insert new TAG/PTE value into data TLB - cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte); - } - break; - - case TheISA::IPR_ITB_IA: - // really a control write - ipr[idx] = 0; - - cpu->itb->flushAll(); - break; - - case TheISA::IPR_ITB_IAP: - // really a control write - ipr[idx] = 0; - - cpu->itb->flushProcesses(); - break; - - case TheISA::IPR_ITB_IS: - // really a control write - ipr[idx] = val; - - cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN])); - break; - - default: - // invalid IPR - return new UnimplementedOpcodeFault; - } - - // no error... - return NoFault; -} - -#endif // #if FULL_SYSTEM - #endif // __CPU_O3_CPU_REGFILE_HH__ |