2 files changed, 11 insertions, 11 deletions

diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 7ec1ba663..c0ec1fb33 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -280,7 +280,7 @@ AlphaFullCPU<Impl>::hwrei()
     uint64_t *ipr = getIpr();
 
     if (!inPalMode())
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
     this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -329,21 +329,21 @@ AlphaFullCPU<Impl>::trap(Fault fault)
     // miss
     uint64_t PC = this->commit.readCommitPC();
 
-    DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
-    this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
+    DPRINTF(Fault, "Fault %s\n", fault->name());
+    this->recordEvent(csprintf("Fault %s", fault->name()));
 
-//    kernelStats.fault(fault);
+    //kernelStats.fault(fault);
 
-    if (fault == ArithmeticFault)
+    if (fault->isA<ArithmeticFault>())
         panic("Arithmetic traps are unimplemented!");
 
     AlphaISA::InternalProcReg *ipr = getIpr();
 
     // exception restart address - Get the commit PC
-    if (fault != InterruptFault || !inPalMode(PC))
+    if (!fault->isA<InterruptFault>() || !inPalMode(PC))
         ipr[AlphaISA::IPR_EXC_ADDR] = PC;
 
-    if (fault == PalFault || fault == ArithmeticFault /* ||
+    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
         fault == InterruptFault && !PC_PAL(regs.pc) */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index ee7b8858e..7e36a6ead 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -372,12 +372,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
       case TheISA::IPR_DTB_IAP:
       case TheISA::IPR_ITB_IA:
       case TheISA::IPR_ITB_IAP:
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
     }
 
@@ -525,7 +525,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
       case TheISA::IPR_ITB_PTE_TEMP:
       case TheISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
       case TheISA::IPR_HWINT_CLR:
       case TheISA::IPR_SL_XMIT:
@@ -627,7 +627,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 
     // no error...