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-rw-r--r--cpu/ozone/cpu.cc34
-rw-r--r--cpu/ozone/cpu.hh629
-rw-r--r--cpu/ozone/cpu_impl.hh1049
-rw-r--r--cpu/ozone/ea_list.cc77
-rw-r--r--cpu/ozone/ea_list.hh72
5 files changed, 0 insertions, 1861 deletions
diff --git a/cpu/ozone/cpu.cc b/cpu/ozone/cpu.cc
deleted file mode 100644
index d2ea0164c..000000000
--- a/cpu/ozone/cpu.cc
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "cpu/ozone/cpu_impl.hh"
-#include "cpu/ozone/ozone_impl.hh"
-#include "cpu/ozone/simple_impl.hh"
-
-template class OzoneCPU<SimpleImpl>;
-template class OzoneCPU<OzoneImpl>;
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
deleted file mode 100644
index 5af2b02b2..000000000
--- a/cpu/ozone/cpu.hh
+++ /dev/null
@@ -1,629 +0,0 @@
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_OZONE_CPU_HH__
-#define __CPU_OZONE_CPU_HH__
-
-#include <set>
-
-#include "base/statistics.hh"
-#include "base/timebuf.hh"
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
-#include "cpu/inst_seq.hh"
-#include "cpu/ozone/rename_table.hh"
-#include "cpu/ozone/thread_state.hh"
-#include "cpu/pc_event.hh"
-#include "cpu/static_inst.hh"
-#include "mem/mem_interface.hh"
-#include "sim/eventq.hh"
-
-// forward declarations
-#if FULL_SYSTEM
-#include "arch/alpha/tlb.hh"
-
-class AlphaITB;
-class AlphaDTB;
-class PhysicalMemory;
-class MemoryController;
-
-class Sampler;
-class RemoteGDB;
-class GDBListener;
-
-namespace Kernel {
- class Statistics;
-};
-
-#else
-
-class Process;
-
-#endif // FULL_SYSTEM
-
-class Checkpoint;
-class EndQuiesceEvent;
-class MemInterface;
-
-namespace Trace {
- class InstRecord;
-}
-
-template <class>
-class Checker;
-
-/**
- * Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with
- * simple out-of-order capabilities added to it. It is still a 1 CPI machine
- * (?), but is capable of handling cache misses. Basically it models having
- * a ROB/IQ by only allowing a certain amount of instructions to execute while
- * the cache miss is outstanding.
- */
-
-template <class Impl>
-class OzoneCPU : public BaseCPU
-{
- private:
- typedef typename Impl::FrontEnd FrontEnd;
- typedef typename Impl::BackEnd BackEnd;
- typedef typename Impl::DynInst DynInst;
- typedef typename Impl::DynInstPtr DynInstPtr;
-
- typedef TheISA::MiscReg MiscReg;
-
- public:
- class OzoneXC : public ExecContext {
- public:
- OzoneCPU<Impl> *cpu;
-
- OzoneThreadState<Impl> *thread;
-
- BaseCPU *getCpuPtr();
-
- void setCpuId(int id);
-
- int readCpuId() { return thread->cpuId; }
-
- FunctionalMemory *getMemPtr() { return thread->mem; }
-
-#if FULL_SYSTEM
- System *getSystemPtr() { return cpu->system; }
-
- PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
-
- AlphaITB *getITBPtr() { return cpu->itb; }
-
- AlphaDTB * getDTBPtr() { return cpu->dtb; }
-
- Kernel::Statistics *getKernelStats() { return thread->kernelStats; }
-#else
- Process *getProcessPtr() { return thread->process; }
-#endif
-
- Status status() const { return thread->_status; }
-
- void setStatus(Status new_status);
-
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- void activate(int delay = 1);
-
- /// Set the status to Suspended.
- void suspend();
-
- /// Set the status to Unallocated.
- void deallocate();
-
- /// Set the status to Halted.
- void halt();
-
-#if FULL_SYSTEM
- void dumpFuncProfile();
-#endif
-
- void takeOverFrom(ExecContext *old_context);
-
- void regStats(const std::string &name);
-
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
-
-#if FULL_SYSTEM
- EndQuiesceEvent *getQuiesceEvent();
-
- Tick readLastActivate();
- Tick readLastSuspend();
-
- void profileClear();
- void profileSample();
-#endif
-
- int getThreadNum();
-
- // Also somewhat obnoxious. Really only used for the TLB fault.
- TheISA::MachInst getInst();
-
- void copyArchRegs(ExecContext *xc);
-
- void clearArchRegs();
-
- uint64_t readIntReg(int reg_idx);
-
- float readFloatRegSingle(int reg_idx);
-
- double readFloatRegDouble(int reg_idx);
-
- uint64_t readFloatRegInt(int reg_idx);
-
- void setIntReg(int reg_idx, uint64_t val);
-
- void setFloatRegSingle(int reg_idx, float val);
-
- void setFloatRegDouble(int reg_idx, double val);
-
- void setFloatRegInt(int reg_idx, uint64_t val);
-
- uint64_t readPC() { return thread->PC; }
- void setPC(Addr val);
-
- uint64_t readNextPC() { return thread->nextPC; }
- void setNextPC(Addr val);
-
- public:
- // ISA stuff:
- MiscReg readMiscReg(int misc_reg);
-
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
-
- Fault setMiscReg(int misc_reg, const MiscReg &val);
-
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
-
- unsigned readStCondFailures()
- { return thread->storeCondFailures; }
-
- void setStCondFailures(unsigned sc_failures)
- { thread->storeCondFailures = sc_failures; }
-
-#if FULL_SYSTEM
- bool inPalMode() { return cpu->inPalMode(); }
-#endif
-
- bool misspeculating() { return false; }
-
-#if !FULL_SYSTEM
- TheISA::IntReg getSyscallArg(int i)
- { return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); }
-
- // used to shift args for indirect syscall
- void setSyscallArg(int i, TheISA::IntReg val)
- { thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
-
- void setSyscallReturn(SyscallReturn return_value)
- { cpu->setSyscallReturn(return_value, thread->tid); }
-
- Counter readFuncExeInst() { return thread->funcExeInst; }
-
- void setFuncExeInst(Counter new_val)
- { thread->funcExeInst = new_val; }
-#endif
- };
-
- // execution context proxy
- OzoneXC ozoneXC;
- ExecContext *xcProxy;
- ExecContext *checkerXC;
-
- typedef OzoneThreadState<Impl> ImplState;
-
- private:
- OzoneThreadState<Impl> thread;
-
- public:
- // main simulation loop (one cycle)
- void tick();
-
- std::set<InstSeqNum> snList;
- std::set<Addr> lockAddrList;
- private:
- struct TickEvent : public Event
- {
- OzoneCPU *cpu;
- int width;
-
- TickEvent(OzoneCPU *c, int w);
- void process();
- const char *description();
- };
-
- TickEvent tickEvent;
-
- /// Schedule tick event, regardless of its current state.
- void scheduleTickEvent(int delay)
- {
- if (tickEvent.squashed())
- tickEvent.reschedule(curTick + cycles(delay));
- else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + cycles(delay));
- }
-
- /// Unschedule tick event, regardless of its current state.
- void unscheduleTickEvent()
- {
- if (tickEvent.scheduled())
- tickEvent.squash();
- }
-
- private:
- Trace::InstRecord *traceData;
-
- template<typename T>
- void trace_data(T data);
-
- public:
- enum Status {
- Running,
- Idle,
- SwitchedOut
- };
-
- Status _status;
-
- public:
- bool checkInterrupts;
-
- void post_interrupt(int int_num, int index);
-
- void zero_fill_64(Addr addr) {
- static int warned = 0;
- if (!warned) {
- warn ("WH64 is not implemented");
- warned = 1;
- }
- };
-
- typedef typename Impl::Params Params;
-
- OzoneCPU(Params *params);
-
- virtual ~OzoneCPU();
-
- void init();
-
- public:
- BaseCPU *getCpuPtr() { return this; }
-
- void setCpuId(int id) { cpuId = id; }
-
- int readCpuId() { return cpuId; }
-
- int cpuId;
-
- void switchOut(Sampler *sampler);
- void signalSwitched();
- void takeOverFrom(BaseCPU *oldCPU);
-
- Sampler *sampler;
-
- int switchCount;
-
-#if FULL_SYSTEM
- Addr dbg_vtophys(Addr addr);
-
- bool interval_stats;
-
- AlphaITB *itb;
- AlphaDTB *dtb;
- System *system;
-
- // the following two fields are redundant, since we can always
- // look them up through the system pointer, but we'll leave them
- // here for now for convenience
- MemoryController *memctrl;
- PhysicalMemory *physmem;
-#endif
-
- // L1 instruction cache
- MemInterface *icacheInterface;
-
- // L1 data cache
- MemInterface *dcacheInterface;
-
- /** Pointer to memory. */
- FunctionalMemory *mem;
-
- FrontEnd *frontEnd;
-
- BackEnd *backEnd;
- private:
- Status status() const { return _status; }
- void setStatus(Status new_status) { _status = new_status; }
-
- virtual void activateContext(int thread_num, int delay);
- virtual void suspendContext(int thread_num);
- virtual void deallocateContext(int thread_num);
- virtual void haltContext(int thread_num);
-
- // statistics
- virtual void regStats();
- virtual void resetStats();
-
- // number of simulated instructions
- public:
- Counter numInst;
- Counter startNumInst;
-
- virtual Counter totalInstructions() const
- {
- return numInst - startNumInst;
- }
-
- private:
- // number of simulated loads
- Counter numLoad;
- Counter startNumLoad;
-
- // number of idle cycles
- Stats::Average<> notIdleFraction;
- Stats::Formula idleFraction;
- public:
-
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-
-#if FULL_SYSTEM
- bool validInstAddr(Addr addr) { return true; }
- bool validDataAddr(Addr addr) { return true; }
-
- Fault translateInstReq(MemReqPtr &req)
- {
- return itb->translate(req);
- }
-
- Fault translateDataReadReq(MemReqPtr &req)
- {
- return dtb->translate(req, false);
- }
-
- Fault translateDataWriteReq(MemReqPtr &req)
- {
- return dtb->translate(req, true);
- }
-
-#else
- bool validInstAddr(Addr addr)
- { return true; }
-
- bool validDataAddr(Addr addr)
- { return true; }
-
- int getInstAsid() { return thread.asid; }
- int getDataAsid() { return thread.asid; }
-
- Fault dummyTranslation(MemReqPtr &req)
- {
-#if 0
- assert((req->vaddr >> 48 & 0xffff) == 0);
-#endif
-
- // put the asid in the upper 16 bits of the paddr
- req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
- req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
- return NoFault;
- }
-
- /** Translates instruction requestion in syscall emulation mode. */
- Fault translateInstReq(MemReqPtr &req)
- {
- return dummyTranslation(req);
- }
-
- /** Translates data read request in syscall emulation mode. */
- Fault translateDataReadReq(MemReqPtr &req)
- {
- return dummyTranslation(req);
- }
-
- /** Translates data write request in syscall emulation mode. */
- Fault translateDataWriteReq(MemReqPtr &req)
- {
- return dummyTranslation(req);
- }
-#endif
-
- /** Old CPU read from memory function. No longer used. */
- template <class T>
- Fault read(MemReqPtr &req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->flags & LOCKED) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-#endif
- Fault error;
- if (req->flags & LOCKED) {
- lockAddrList.insert(req->paddr);
- lockFlag = true;
- }
-
- error = this->mem->read(req, data);
- data = gtoh(data);
- return error;
- }
-
-
- /** CPU read function, forwards read to LSQ. */
- template <class T>
- Fault read(MemReqPtr &req, T &data, int load_idx)
- {
- return backEnd->read(req, data, load_idx);
- }
-
- /** Old CPU write to memory function. No longer used. */
- template <class T>
- Fault write(MemReqPtr &req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->flags & LOCKED) {
- xc = req->xc;
-
- if (req->flags & UNCACHEABLE) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < this->system->execContexts.size(); i++){
- xc = this->system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
-#endif
-
- if (req->flags & LOCKED) {
- if (req->flags & UNCACHEABLE) {
- req->result = 2;
- } else {
- if (this->lockFlag) {
- if (lockAddrList.find(req->paddr) !=
- lockAddrList.end()) {
- req->result = 1;
- } else {
- req->result = 0;
- return NoFault;
- }
- } else {
- req->result = 0;
- return NoFault;
- }
- }
- }
-
- return this->mem->write(req, (T)htog(data));
- }
-
- /** CPU write function, forwards write to LSQ. */
- template <class T>
- Fault write(MemReqPtr &req, T &data, int store_idx)
- {
- return backEnd->write(req, data, store_idx);
- }
-
- void prefetch(Addr addr, unsigned flags)
- {
- // need to do this...
- }
-
- void writeHint(Addr addr, int size, unsigned flags)
- {
- // need to do this...
- }
-
- Fault copySrcTranslate(Addr src);
-
- Fault copy(Addr dest);
-
- InstSeqNum globalSeqNum;
-
- public:
- void squashFromXC();
-
- // @todo: This can be a useful debug function. Implement it.
- void dumpInsts() { frontEnd->dumpInsts(); }
-
-#if FULL_SYSTEM
- Fault hwrei();
- int readIntrFlag() { return thread.regs.intrflag; }
- void setIntrFlag(int val) { thread.regs.intrflag = val; }
- bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
- bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
- bool simPalCheck(int palFunc);
- void processInterrupts();
-#else
- void syscall();
- void setSyscallReturn(SyscallReturn return_value, int tid);
-#endif
-
- ExecContext *xcBase() { return xcProxy; }
-
- bool decoupledFrontEnd;
- struct CommStruct {
- InstSeqNum doneSeqNum;
- InstSeqNum nonSpecSeqNum;
- bool uncached;
- unsigned lqIdx;
-
- bool stall;
- };
- TimeBuffer<CommStruct> comm;
-
- bool lockFlag;
-
- Stats::Scalar<> quiesceCycles;
-
- Checker<DynInstPtr> *checker;
-};
-
-#endif // __CPU_OZONE_CPU_HH__
diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh
deleted file mode 100644
index 5675da3a8..000000000
--- a/cpu/ozone/cpu_impl.hh
+++ /dev/null
@@ -1,1049 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-//#include <cstdio>
-//#include <cstdlib>
-
-#include "arch/isa_traits.hh" // For MachInst
-#include "base/trace.hh"
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/checker/exec_context.hh"
-#include "cpu/exec_context.hh"
-#include "cpu/exetrace.hh"
-#include "cpu/ozone/cpu.hh"
-#include "cpu/quiesce_event.hh"
-#include "cpu/static_inst.hh"
-//#include "mem/base_mem.hh"
-#include "mem/mem_interface.hh"
-#include "sim/sim_object.hh"
-#include "sim/stats.hh"
-
-#if FULL_SYSTEM
-#include "arch/faults.hh"
-#include "arch/alpha/osfpal.hh"
-#include "arch/alpha/tlb.hh"
-#include "arch/vtophys.hh"
-#include "base/callback.hh"
-//#include "base/remote_gdb.hh"
-#include "cpu/profile.hh"
-#include "kern/kernel_stats.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
-#include "sim/faults.hh"
-#include "sim/sim_events.hh"
-#include "sim/sim_exit.hh"
-#include "sim/system.hh"
-#else // !FULL_SYSTEM
-#include "mem/functional/functional.hh"
-#include "sim/process.hh"
-#endif // FULL_SYSTEM
-
-using namespace TheISA;
-
-template <class Impl>
-template<typename T>
-void
-OzoneCPU<Impl>::trace_data(T data) {
- if (traceData) {
- traceData->setData(data);
- }
-}
-
-template <class Impl>
-OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
- : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
-{
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::TickEvent::process()
-{
- cpu->tick();
-}
-
-template <class Impl>
-const char *
-OzoneCPU<Impl>::TickEvent::description()
-{
- return "OzoneCPU tick event";
-}
-
-template <class Impl>
-OzoneCPU<Impl>::OzoneCPU(Params *p)
-#if FULL_SYSTEM
- : BaseCPU(p), thread(this, 0, p->mem), tickEvent(this, p->width),
- mem(p->mem),
-#else
- : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width),
- mem(p->workload[0]->getMemory()),
-#endif
- comm(5, 5)
-{
- frontEnd = new FrontEnd(p);
- backEnd = new BackEnd(p);
-
- _status = Idle;
-
- if (p->checker) {
- BaseCPU *temp_checker = p->checker;
- checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
- checker->setMemory(mem);
-#if FULL_SYSTEM
- checker->setSystem(p->system);
-#endif
- checkerXC = new CheckerExecContext<OzoneXC>(&ozoneXC, checker);
- thread.xcProxy = checkerXC;
- xcProxy = checkerXC;
- } else {
- checker = NULL;
- thread.xcProxy = &ozoneXC;
- xcProxy = &ozoneXC;
- }
-
- ozoneXC.cpu = this;
- ozoneXC.thread = &thread;
-
- thread.inSyscall = false;
-
- thread.setStatus(ExecContext::Suspended);
-#if FULL_SYSTEM
- /***** All thread state stuff *****/
- thread.cpu = this;
- thread.tid = 0;
- thread.mem = p->mem;
-
- thread.quiesceEvent = new EndQuiesceEvent(xcProxy);
-
- system = p->system;
- itb = p->itb;
- dtb = p->dtb;
- memctrl = p->system->memctrl;
- physmem = p->system->physmem;
-
- if (p->profile) {
- thread.profile = new FunctionProfile(p->system->kernelSymtab);
- // @todo: This might be better as an ExecContext instead of OzoneXC
- Callback *cb =
- new MakeCallback<OzoneXC,
- &OzoneXC::dumpFuncProfile>(&ozoneXC);
- registerExitCallback(cb);
- }
-
- // let's fill with a dummy node for now so we don't get a segfault
- // on the first cycle when there's no node available.
- static ProfileNode dummyNode;
- thread.profileNode = &dummyNode;
- thread.profilePC = 3;
-#else
- thread.cpu = this;
- thread.tid = 0;
- thread.process = p->workload[0];
- thread.asid = 0;
-#endif // !FULL_SYSTEM
-
- numInst = 0;
- startNumInst = 0;
-
- execContexts.push_back(xcProxy);
-
- frontEnd->setCPU(this);
- backEnd->setCPU(this);
-
- frontEnd->setXC(xcProxy);
- backEnd->setXC(xcProxy);
-
- frontEnd->setThreadState(&thread);
- backEnd->setThreadState(&thread);
-
- frontEnd->setCommBuffer(&comm);
- backEnd->setCommBuffer(&comm);
-
- frontEnd->setBackEnd(backEnd);
- backEnd->setFrontEnd(frontEnd);
-
- decoupledFrontEnd = p->decoupledFrontEnd;
-
- globalSeqNum = 1;
-
- checkInterrupts = false;
-
- for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
- thread.renameTable[i] = new DynInst(this);
- thread.renameTable[i]->setResultReady();
- }
-
- frontEnd->renameTable.copyFrom(thread.renameTable);
- backEnd->renameTable.copyFrom(thread.renameTable);
-
-#if !FULL_SYSTEM
-// pTable = p->pTable;
-#endif
-
- lockFlag = 0;
-
- DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
-}
-
-template <class Impl>
-OzoneCPU<Impl>::~OzoneCPU()
-{
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::switchOut(Sampler *_sampler)
-{
- sampler = _sampler;
- switchCount = 0;
- // Front end needs state from back end, so switch out the back end first.
- backEnd->switchOut();
- frontEnd->switchOut();
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::signalSwitched()
-{
- if (++switchCount == 2) {
- backEnd->doSwitchOut();
- frontEnd->doSwitchOut();
- if (checker)
- checker->switchOut(sampler);
- _status = SwitchedOut;
- if (tickEvent.scheduled())
- tickEvent.squash();
- sampler->signalSwitched();
- }
- assert(switchCount <= 2);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
-{
- BaseCPU::takeOverFrom(oldCPU);
-
- backEnd->takeOverFrom();
- frontEnd->takeOverFrom();
- assert(!tickEvent.scheduled());
-
- // @todo: Fix hardcoded number
- // Clear out any old information in time buffer.
- for (int i = 0; i < 6; ++i) {
- comm.advance();
- }
-
- // if any of this CPU's ExecContexts are active, mark the CPU as
- // running and schedule its tick event.
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
- if (xc->status() == ExecContext::Active &&
- _status != Running) {
- _status = Running;
- tickEvent.schedule(curTick);
- }
- }
- // Nothing running, change status to reflect that we're no longer
- // switched out.
- if (_status == SwitchedOut) {
- _status = Idle;
- }
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::activateContext(int thread_num, int delay)
-{
- // Eventually change this in SMT.
- assert(thread_num == 0);
-
- assert(_status == Idle);
- notIdleFraction++;
- scheduleTickEvent(delay);
- _status = Running;
- thread._status = ExecContext::Active;
- frontEnd->wakeFromQuiesce();
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::suspendContext(int thread_num)
-{
- // Eventually change this in SMT.
- assert(thread_num == 0);
- // @todo: Figure out how to initially set the status properly so
- // this is running.
-// assert(_status == Running);
- notIdleFraction--;
- unscheduleTickEvent();
- _status = Idle;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::deallocateContext(int thread_num)
-{
- // for now, these are equivalent
- suspendContext(thread_num);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::haltContext(int thread_num)
-{
- // for now, these are equivalent
- suspendContext(thread_num);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::regStats()
-{
- using namespace Stats;
-
- BaseCPU::regStats();
-
- thread.numInsts
- .name(name() + ".num_insts")
- .desc("Number of instructions executed")
- ;
-
- thread.numMemRefs
- .name(name() + ".num_refs")
- .desc("Number of memory references")
- ;
-
- notIdleFraction
- .name(name() + ".not_idle_fraction")
- .desc("Percentage of non-idle cycles")
- ;
-
- idleFraction
- .name(name() + ".idle_fraction")
- .desc("Percentage of idle cycles")
- ;
-
- quiesceCycles
- .name(name() + ".quiesce_cycles")
- .desc("Number of cycles spent in quiesce")
- ;
-
- idleFraction = constant(1.0) - notIdleFraction;
-
- frontEnd->regStats();
- backEnd->regStats();
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::resetStats()
-{
- startNumInst = numInst;
- notIdleFraction = (_status != Idle);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::init()
-{
- BaseCPU::init();
-
- // Mark this as in syscall so it won't need to squash
- thread.inSyscall = true;
-#if FULL_SYSTEM
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
-
- // initialize CPU, including PC
- TheISA::initCPU(xc, xc->readCpuId());
- }
-#endif
- frontEnd->renameTable.copyFrom(thread.renameTable);
- backEnd->renameTable.copyFrom(thread.renameTable);
-
- thread.inSyscall = false;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::serialize(std::ostream &os)
-{
- BaseCPU::serialize(os);
- SERIALIZE_ENUM(_status);
- nameOut(os, csprintf("%s.xc", name()));
- ozoneXC.serialize(os);
- nameOut(os, csprintf("%s.tickEvent", name()));
- tickEvent.serialize(os);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
-{
- BaseCPU::unserialize(cp, section);
- UNSERIALIZE_ENUM(_status);
- ozoneXC.unserialize(cp, csprintf("%s.xc", section));
- tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
-}
-
-template <class Impl>
-Fault
-OzoneCPU<Impl>::copySrcTranslate(Addr src)
-{
- panic("Copy not implemented!\n");
- return NoFault;
-#if 0
- static bool no_warn = true;
- int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
- // Only support block sizes of 64 atm.
- assert(blk_size == 64);
- int offset = src & (blk_size - 1);
-
- // Make sure block doesn't span page
- if (no_warn &&
- (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
- (src >> 40) != 0xfffffc) {
- warn("Copied block source spans pages %x.", src);
- no_warn = false;
- }
-
- memReq->reset(src & ~(blk_size - 1), blk_size);
-
- // translate to physical address
- Fault fault = xc->translateDataReadReq(memReq);
-
- assert(fault != Alignment_Fault);
-
- if (fault == NoFault) {
- xc->copySrcAddr = src;
- xc->copySrcPhysAddr = memReq->paddr + offset;
- } else {
- xc->copySrcAddr = 0;
- xc->copySrcPhysAddr = 0;
- }
- return fault;
-#endif
-}
-
-template <class Impl>
-Fault
-OzoneCPU<Impl>::copy(Addr dest)
-{
- panic("Copy not implemented!\n");
- return NoFault;
-#if 0
- static bool no_warn = true;
- int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
- // Only support block sizes of 64 atm.
- assert(blk_size == 64);
- uint8_t data[blk_size];
- //assert(xc->copySrcAddr);
- int offset = dest & (blk_size - 1);
-
- // Make sure block doesn't span page
- if (no_warn &&
- (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
- (dest >> 40) != 0xfffffc) {
- no_warn = false;
- warn("Copied block destination spans pages %x. ", dest);
- }
-
- memReq->reset(dest & ~(blk_size -1), blk_size);
- // translate to physical address
- Fault fault = xc->translateDataWriteReq(memReq);
-
- assert(fault != Alignment_Fault);
-
- if (fault == NoFault) {
- Addr dest_addr = memReq->paddr + offset;
- // Need to read straight from memory since we have more than 8 bytes.
- memReq->paddr = xc->copySrcPhysAddr;
- xc->mem->read(memReq, data);
- memReq->paddr = dest_addr;
- xc->mem->write(memReq, data);
- if (dcacheInterface) {
- memReq->cmd = Copy;
- memReq->completionEvent = NULL;
- memReq->paddr = xc->copySrcPhysAddr;
- memReq->dest = dest_addr;
- memReq->size = 64;
- memReq->time = curTick;
- dcacheInterface->access(memReq);
- }
- }
- return fault;
-#endif
-}
-
-#if FULL_SYSTEM
-template <class Impl>
-Addr
-OzoneCPU<Impl>::dbg_vtophys(Addr addr)
-{
- return vtophys(xcProxy, addr);
-}
-#endif // FULL_SYSTEM
-
-#if FULL_SYSTEM
-template <class Impl>
-void
-OzoneCPU<Impl>::post_interrupt(int int_num, int index)
-{
- BaseCPU::post_interrupt(int_num, index);
-
- if (_status == Idle) {
- DPRINTF(IPI,"Suspended Processor awoke\n");
-// thread.activate();
- // Hack for now. Otherwise might have to go through the xcProxy, or
- // I need to figure out what's the right thing to call.
- activateContext(thread.tid, 1);
- }
-}
-#endif // FULL_SYSTEM
-
-/* start simulation, program loaded, processor precise state initialized */
-template <class Impl>
-void
-OzoneCPU<Impl>::tick()
-{
- DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
-
- _status = Running;
- thread.renameTable[ZeroReg]->setIntResult(0);
- thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
- setDoubleResult(0.0);
-
- comm.advance();
- frontEnd->tick();
- backEnd->tick();
-
- // check for instruction-count-based events
- comInstEventQueue[0]->serviceEvents(numInst);
-
- if (!tickEvent.scheduled() && _status == Running)
- tickEvent.schedule(curTick + cycles(1));
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::squashFromXC()
-{
- thread.inSyscall = true;
- backEnd->generateXCEvent();
-}
-
-#if !FULL_SYSTEM
-template <class Impl>
-void
-OzoneCPU<Impl>::syscall()
-{
- // Not sure this copy is needed, depending on how the XC proxy is made.
- thread.renameTable.copyFrom(backEnd->renameTable);
-
- thread.inSyscall = true;
-
- thread.funcExeInst++;
-
- DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
-
- thread.process->syscall(xcProxy);
-
- thread.funcExeInst--;
-
- thread.inSyscall = false;
-
- frontEnd->renameTable.copyFrom(thread.renameTable);
- backEnd->renameTable.copyFrom(thread.renameTable);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
-{
- // check for error condition. Alpha syscall convention is to
- // indicate success/failure in reg a3 (r19) and put the
- // return value itself in the standard return value reg (v0).
- if (return_value.successful()) {
- // no error
- thread.renameTable[SyscallSuccessReg]->setIntResult(0);
- thread.renameTable[ReturnValueReg]->setIntResult(
- return_value.value());
- } else {
- // got an error, return details
- thread.renameTable[SyscallSuccessReg]->setIntResult((IntReg) -1);
- thread.renameTable[ReturnValueReg]->setIntResult(
- -return_value.value());
- }
-}
-#else
-template <class Impl>
-Fault
-OzoneCPU<Impl>::hwrei()
-{
- // Need to move this to ISA code
- // May also need to make this per thread
-
- lockFlag = false;
- lockAddrList.clear();
- thread.kernelStats->hwrei();
-
- checkInterrupts = true;
-
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::processInterrupts()
-{
- // Check for interrupts here. For now can copy the code that
- // exists within isa_fullsys_traits.hh. Also assume that thread 0
- // is the one that handles the interrupts.
-
- // Check if there are any outstanding interrupts
- //Handle the interrupts
- int ipl = 0;
- int summary = 0;
-
- checkInterrupts = false;
-
- if (thread.readMiscReg(IPR_ASTRR))
- panic("asynchronous traps not implemented\n");
-
- if (thread.readMiscReg(IPR_SIRR)) {
- for (int i = INTLEVEL_SOFTWARE_MIN;
- i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (thread.readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
- // See table 4-19 of the 21164 hardware reference
- ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- uint64_t interrupts = intr_status();
-
- if (interrupts) {
- for (int i = INTLEVEL_EXTERNAL_MIN;
- i < INTLEVEL_EXTERNAL_MAX; i++) {
- if (interrupts & (ULL(1) << i)) {
- // See table 4-19 of the 21164 hardware reference
- ipl = i;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) {
- thread.setMiscReg(IPR_ISR, summary);
- thread.setMiscReg(IPR_INTID, ipl);
- // @todo: Make this more transparent
- if (checker) {
- checker->cpuXCBase()->setMiscReg(IPR_ISR, summary);
- checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl);
- }
- Fault fault = new InterruptFault;
- fault->invoke(thread.getXCProxy());
- DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- thread.readMiscReg(IPR_IPLR), ipl, summary);
- }
-}
-
-template <class Impl>
-bool
-OzoneCPU<Impl>::simPalCheck(int palFunc)
-{
- // Need to move this to ISA code
- // May also need to make this per thread
- thread.kernelStats->callpal(palFunc, xcProxy);
-
- switch (palFunc) {
- case PAL::halt:
- haltContext(thread.tid);
- if (--System::numSystemsRunning == 0)
- new SimExitEvent("all cpus halted");
- break;
-
- case PAL::bpt:
- case PAL::bugchk:
- if (system->breakpoint())
- return false;
- break;
- }
-
- return true;
-}
-#endif
-
-template <class Impl>
-BaseCPU *
-OzoneCPU<Impl>::OzoneXC::getCpuPtr()
-{
- return cpu;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setCpuId(int id)
-{
- cpu->cpuId = id;
- thread->cpuId = id;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setStatus(Status new_status)
-{
- thread->_status = new_status;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::activate(int delay)
-{
- cpu->activateContext(thread->tid, delay);
-}
-
-/// Set the status to Suspended.
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::suspend()
-{
- cpu->suspendContext(thread->tid);
-}
-
-/// Set the status to Unallocated.
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::deallocate()
-{
- cpu->deallocateContext(thread->tid);
-}
-
-/// Set the status to Halted.
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::halt()
-{
- cpu->haltContext(thread->tid);
-}
-
-#if FULL_SYSTEM
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::dumpFuncProfile()
-{ }
-#endif
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
-{
- // some things should already be set up
- assert(getMemPtr() == old_context->getMemPtr());
-#if FULL_SYSTEM
- assert(getSystemPtr() == old_context->getSystemPtr());
-#else
- assert(getProcessPtr() == old_context->getProcessPtr());
-#endif
-
- // copy over functional state
- setStatus(old_context->status());
- copyArchRegs(old_context);
- setCpuId(old_context->readCpuId());
-
-#if !FULL_SYSTEM
- setFuncExeInst(old_context->readFuncExeInst());
-#else
- EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
- if (other_quiesce) {
- // Point the quiesce event's XC at this XC so that it wakes up
- // the proper CPU.
- other_quiesce->xc = this;
- }
- if (thread->quiesceEvent) {
- thread->quiesceEvent->xc = this;
- }
-
- thread->kernelStats = old_context->getKernelStats();
-// storeCondFailures = 0;
- cpu->lockFlag = false;
-#endif
-
- old_context->setStatus(ExecContext::Unallocated);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name)
-{
-#if FULL_SYSTEM
- thread->kernelStats = new Kernel::Statistics(cpu->system);
- thread->kernelStats->regStats(name + ".kern");
-#endif
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::serialize(std::ostream &os)
-{ }
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::unserialize(Checkpoint *cp, const std::string &section)
-{ }
-
-#if FULL_SYSTEM
-template <class Impl>
-EndQuiesceEvent *
-OzoneCPU<Impl>::OzoneXC::getQuiesceEvent()
-{
- return thread->quiesceEvent;
-}
-
-template <class Impl>
-Tick
-OzoneCPU<Impl>::OzoneXC::readLastActivate()
-{
- return thread->lastActivate;
-}
-
-template <class Impl>
-Tick
-OzoneCPU<Impl>::OzoneXC::readLastSuspend()
-{
- return thread->lastSuspend;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::profileClear()
-{
- if (thread->profile)
- thread->profile->clear();
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::profileSample()
-{
- if (thread->profile)
- thread->profile->sample(thread->profileNode, thread->profilePC);
-}
-#endif
-
-template <class Impl>
-int
-OzoneCPU<Impl>::OzoneXC::getThreadNum()
-{
- return thread->tid;
-}
-
-// Also somewhat obnoxious. Really only used for the TLB fault.
-template <class Impl>
-TheISA::MachInst
-OzoneCPU<Impl>::OzoneXC::getInst()
-{
- return thread->inst;
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::copyArchRegs(ExecContext *xc)
-{
- thread->PC = xc->readPC();
- thread->nextPC = xc->readNextPC();
-
- cpu->frontEnd->setPC(thread->PC);
- cpu->frontEnd->setNextPC(thread->nextPC);
-
- for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
- if (i < TheISA::FP_Base_DepTag) {
- thread->renameTable[i]->setIntResult(xc->readIntReg(i));
- } else if (i < (TheISA::FP_Base_DepTag + TheISA::NumFloatRegs)) {
- int fp_idx = i - TheISA::FP_Base_DepTag;
- thread->renameTable[i]->setDoubleResult(
- xc->readFloatRegDouble(fp_idx));
- }
- }
-
-#if !FULL_SYSTEM
- thread->funcExeInst = xc->readFuncExeInst();
-#endif
-
- // Need to copy the XC values into the current rename table,
- // copy the misc regs.
- thread->regs.miscRegs.copyMiscRegs(xc);
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::clearArchRegs()
-{
- panic("Unimplemented!");
-}
-
-template <class Impl>
-uint64_t
-OzoneCPU<Impl>::OzoneXC::readIntReg(int reg_idx)
-{
- return thread->renameTable[reg_idx]->readIntResult();
-}
-
-template <class Impl>
-float
-OzoneCPU<Impl>::OzoneXC::readFloatRegSingle(int reg_idx)
-{
- int idx = reg_idx + TheISA::FP_Base_DepTag;
- return thread->renameTable[idx]->readFloatResult();
-}
-
-template <class Impl>
-double
-OzoneCPU<Impl>::OzoneXC::readFloatRegDouble(int reg_idx)
-{
- int idx = reg_idx + TheISA::FP_Base_DepTag;
- return thread->renameTable[idx]->readDoubleResult();
-}
-
-template <class Impl>
-uint64_t
-OzoneCPU<Impl>::OzoneXC::readFloatRegInt(int reg_idx)
-{
- int idx = reg_idx + TheISA::FP_Base_DepTag;
- return thread->renameTable[idx]->readIntResult();
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setIntReg(int reg_idx, uint64_t val)
-{
- thread->renameTable[reg_idx]->setIntResult(val);
-
- if (!thread->inSyscall) {
- cpu->squashFromXC();
- }
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setFloatRegSingle(int reg_idx, float val)
-{
- panic("Unimplemented!");
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setFloatRegDouble(int reg_idx, double val)
-{
- int idx = reg_idx + TheISA::FP_Base_DepTag;
-
- thread->renameTable[idx]->setDoubleResult(val);
-
- if (!thread->inSyscall) {
- cpu->squashFromXC();
- }
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setFloatRegInt(int reg_idx, uint64_t val)
-{
- panic("Unimplemented!");
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setPC(Addr val)
-{
- thread->PC = val;
- cpu->frontEnd->setPC(val);
-
- if (!thread->inSyscall) {
- cpu->squashFromXC();
- }
-}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneXC::setNextPC(Addr val)
-{
- thread->nextPC = val;
- cpu->frontEnd->setNextPC(val);
-
- if (!thread->inSyscall) {
- cpu->squashFromXC();
- }
-}
-
-template <class Impl>
-TheISA::MiscReg
-OzoneCPU<Impl>::OzoneXC::readMiscReg(int misc_reg)
-{
- return thread->regs.miscRegs.readReg(misc_reg);
-}
-
-template <class Impl>
-TheISA::MiscReg
-OzoneCPU<Impl>::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault)
-{
- return thread->regs.miscRegs.readRegWithEffect(misc_reg,
- fault, this);
-}
-
-template <class Impl>
-Fault
-OzoneCPU<Impl>::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val)
-{
- // Needs to setup a squash event unless we're in syscall mode
- Fault ret_fault = thread->regs.miscRegs.setReg(misc_reg, val);
-
- if (!thread->inSyscall) {
- cpu->squashFromXC();
- }
-
- return ret_fault;
-}
-
-template <class Impl>
-Fault
-OzoneCPU<Impl>::OzoneXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-{
- // Needs to setup a squash event unless we're in syscall mode
- Fault ret_fault = thread->regs.miscRegs.setRegWithEffect(misc_reg, val,
- this);
-
- if (!thread->inSyscall) {
- cpu->squashFromXC();
- }
-
- return ret_fault;
-}
diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc
deleted file mode 100644
index 6114a0ca1..000000000
--- a/cpu/ozone/ea_list.cc
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/isa_traits.hh"
-#include "cpu/inst_seq.hh"
-#include "cpu/ooo_cpu/ea_list.hh"
-
-void
-EAList::addAddr(const InstSeqNum &new_sn, const Addr &new_ea)
-{
- instEA newEA(new_sn, new_ea);
-
- eaList.push_back(newEA);
-}
-
-void
-EAList::clearAddr(const InstSeqNum &sn_to_clear, const Addr &ea_to_clear)
-{
- eaListIt list_it = eaList.begin();
-
- while (list_it != eaList.end() && (*list_it).first != sn_to_clear) {
- assert((*list_it).second == ea_to_clear);
- }
-}
-
-bool
-EAList::checkConflict(const InstSeqNum &check_sn, const Addr &check_ea) const
-{
- const constEAListIt list_it = eaList.begin();
-
- while (list_it != eaList.end() && (*list_it).first < check_sn) {
- if ((*list_it).second == check_ea) {
- return true;
- }
- }
-
- return false;
-}
-
-void
-EAList::clear()
-{
- eaList.clear();
-}
-
-void
-EAList::commit(const InstSeqNum &commit_sn)
-{
- while (!eaList.empty() && eaList.front().first <= commit_sn) {
- eaList.pop_front();
- }
-}
diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh
deleted file mode 100644
index c0eee4bb8..000000000
--- a/cpu/ozone/ea_list.hh
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_EA_LIST_HH__
-#define __CPU_EA_LIST_HH__
-
-#include <list>
-#include <utility>
-
-#include "arch/isa_traits.hh"
-#include "cpu/inst_seq.hh"
-
-/**
- * Simple class to hold onto a list of pairs, each pair having a memory
- * instruction's sequence number and effective addr. This list can be used
- * for memory disambiguation. However, if I ever want to forward results, I
- * may have to use a list that holds DynInstPtrs. Hence this may change in
- * the future.
- */
-class EAList {
- private:
- typedef std::pair<InstSeqNum, Addr> instEA;
- typedef std::list<instEA>::iterator eaListIt;
- typedef std::list<instEA>::const_iterator constEAListIt;
-
- std::list<instEA> eaList;
-
- public:
- EAList() { }
- ~EAList() { }
-
- void addAddr(const InstSeqNum &new_sn, const Addr &new_ea);
-
- void clearAddr(const InstSeqNum &sn_to_clear, const Addr &ea_to_clear);
-
- /** Checks if any instructions older than check_sn have a conflicting
- * address with check_ea. Note that this function does not handle the
- * sequence number rolling over.
- */
- bool checkConflict(const InstSeqNum &check_sn, const Addr &check_ea) const;
-
- void clear();
-
- void commit(const InstSeqNum &commit_sn);
-};
-
-#endif // __CPU_EA_LIST_HH__
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