diff options
Diffstat (limited to 'cpu/ozone')
-rw-r--r-- | cpu/ozone/cpu.hh | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh index 7976632d9..667e2b3f8 100644 --- a/cpu/ozone/cpu.hh +++ b/cpu/ozone/cpu.hh @@ -285,17 +285,17 @@ class OoOCPU : public BaseCPU int getInstAsid() { return xc->regs.instAsid(); } int getDataAsid() { return xc->regs.dataAsid(); } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -310,7 +310,7 @@ class OoOCPU : public BaseCPU int getInstAsid() { return xc->asid; } int getDataAsid() { return xc->asid; } - Fault * dummyTranslation(MemReqPtr &req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -321,15 +321,15 @@ class OoOCPU : public BaseCPU req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; return NoFault; } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -337,10 +337,10 @@ class OoOCPU : public BaseCPU #endif template <class T> - Fault * read(Addr addr, T &data, unsigned flags, DynInstPtr inst); + Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst); template <class T> - Fault * write(T data, Addr addr, unsigned flags, + Fault write(T data, Addr addr, unsigned flags, uint64_t *res, DynInstPtr inst); void prefetch(Addr addr, unsigned flags) @@ -353,9 +353,9 @@ class OoOCPU : public BaseCPU // need to do this... } - Fault * copySrcTranslate(Addr src); + Fault copySrcTranslate(Addr src); - Fault * copy(Addr dest); + Fault copy(Addr dest); private: bool executeInst(DynInstPtr &inst); @@ -368,7 +368,7 @@ class OoOCPU : public BaseCPU bool getOneInst(); - Fault * fetchCacheLine(); + Fault fetchCacheLine(); InstSeqNum getAndIncrementInstSeq(); @@ -511,13 +511,13 @@ class OoOCPU : public BaseCPU void setFpcr(uint64_t val) { xc->setFpcr(val); } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); } - Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } - Fault * hwrei() { return xc->hwrei(); } + uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } + Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } + Fault hwrei() { return xc->hwrei(); } int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault * fault) { xc->ev5_trap(fault); } + void ev5_trap(Fault fault) { xc->ev5_trap(fault); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } @@ -530,7 +530,7 @@ class OoOCPU : public BaseCPU // precise architected memory state accessor macros template <class Impl> template <class T> -Fault * +Fault OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst) { MemReqPtr readReq = new MemReq(); @@ -541,7 +541,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst) readReq->reset(addr, sizeof(T), flags); // translate to physical address - This might be an ISA impl call - Fault * fault = translateDataReadReq(readReq); + Fault fault = translateDataReadReq(readReq); // do functional access if (fault == NoFault) @@ -575,7 +575,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst) template <class Impl> template <class T> -Fault * +Fault OoOCPU<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res, DynInstPtr inst) { @@ -594,7 +594,7 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags, writeReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault * fault = translateDataWriteReq(writeReq); + Fault fault = translateDataWriteReq(writeReq); // do functional access if (fault == NoFault) |