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-rw-r--r--cpu/simple/cpu.cc87
1 files changed, 46 insertions, 41 deletions
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index d188074d4..261ed8302 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -64,8 +64,8 @@
#if FULL_SYSTEM
#include "base/remote_gdb.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
+//#include "mem/functional/memory_control.hh"
+//#include "mem/functional/physical.hh"
#include "sim/system.hh"
#include "arch/tlb.hh"
#include "arch/stacktrace.hh"
@@ -86,6 +86,15 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
void
SimpleCPU::init()
{
+ //Create Memory Ports (conect them up)
+ Port *mem_dport = mem->getPort("");
+ dcachePort.setPeer(mem_dport);
+ mem_dport->setPeer(&dcachePort);
+
+ Port *mem_iport = mem->getPort("");
+ icachePort.setPeer(mem_iport);
+ mem_iport->setPeer(&icachePort);
+
BaseCPU::init();
#if FULL_SYSTEM
for (int i = 0; i < execContexts.size(); ++i) {
@@ -146,48 +155,44 @@ SimpleCPU::CpuPort::recvRetry()
}
SimpleCPU::SimpleCPU(Params *p)
- : BaseCPU(p), icachePort(this),
+#if !FULL_SYSTEM
+ : BaseCPU(p), mem(p->mem), icachePort(this),
dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
+#else
+ : BaseCPU(p), icachePort(this), dcachePort(this),
+ tickEvent(this, p->width), cpuXC(NULL)
+#endif
{
_status = Idle;
- //Create Memory Ports (conect them up)
- Port *mem_dport = p->mem->getPort();
- dcachePort.setPeer(mem_dport);
- mem_dport->setPeer(&dcachePort);
-
- Port *mem_iport = p->mem->getPort();
- icachePort.setPeer(mem_iport);
- mem_iport->setPeer(&icachePort);
-
#if FULL_SYSTEM
- cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
+ cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
#else
- cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0,
- &dcachePort);
+ cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
+ /* asid */ 0, mem);
#endif // !FULL_SYSTEM
xcProxy = cpuXC->getProxy();
#if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
- ifetch_req = new CpuRequest;
- ifetch_req->asid = 0;
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req = new Request(true);
+ ifetch_req->setAsid(0);
+ ifetch_req->setSize(sizeof(MachInst));
ifetch_pkt = new Packet;
ifetch_pkt->cmd = Read;
ifetch_pkt->data = (uint8_t *)&inst;
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
- data_read_req = new CpuRequest;
- data_read_req->asid = 0;
+ data_read_req = new Request(true);
+ data_read_req->setAsid(0);
data_read_pkt = new Packet;
data_read_pkt->cmd = Read;
data_read_pkt->data = new uint8_t[8];
data_read_pkt->req = data_read_req;
- data_write_req = new CpuRequest;
- data_write_req->asid = 0;
+ data_write_req = new Request(true);
+ data_write_req->setAsid(0);
data_write_pkt = new Packet;
data_write_pkt->cmd = Write;
data_write_pkt->req = data_write_req;
@@ -488,13 +493,13 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
// memReq->reset(addr, sizeof(T), flags);
#if SIMPLE_CPU_MEM_TIMING
- CpuRequest *data_read_req = new CpuRequest;
+ CpuRequest *data_read_req = new Request(true);
#endif
- data_read_req->vaddr = addr;
- data_read_req->size = sizeof(T);
- data_read_req->flags = flags;
- data_read_req->time = curTick;
+ data_read_req->setVaddr(addr);
+ data_read_req->setSize(sizeof(T));
+ data_read_req->setFlags(flags);
+ data_read_req->setTime(curTick);
// translate to physical address
Fault fault = cpuXC->translateDataReadReq(data_read_req);
@@ -507,7 +512,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
data_read_pkt->req = data_read_req;
data_read_pkt->data = new uint8_t[8];
#endif
- data_read_pkt->addr = data_read_req->paddr;
+ data_read_pkt->addr = data_read_req->getPaddr();
data_read_pkt->size = sizeof(T);
sendDcacheRequest(data_read_pkt);
@@ -554,7 +559,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
}
*/
// This will need a new way to tell if it has a dcache attached.
- if (data_read_req->flags & UNCACHEABLE)
+ if (data_read_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Read");
return fault;
@@ -607,10 +612,10 @@ template <class T>
Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- data_write_req->vaddr = addr;
- data_write_req->time = curTick;
- data_write_req->size = sizeof(T);
- data_write_req->flags = flags;
+ data_write_req->setVaddr(addr);
+ data_write_req->setTime(curTick);
+ data_write_req->setSize(sizeof(T));
+ data_write_req->setFlags(flags);
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
@@ -625,7 +630,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#else
data_write_pkt->data = (uint8_t *)&data;
#endif
- data_write_pkt->addr = data_write_req->paddr;
+ data_write_pkt->addr = data_write_req->getPaddr();
data_write_pkt->size = sizeof(T);
sendDcacheRequest(data_write_pkt);
@@ -659,7 +664,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
*res = data_write_pkt->result;
// This will need a new way to tell if it's hooked up to a cache or not.
- if (data_write_req->flags & UNCACHEABLE)
+ if (data_write_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Write");
// If the write needs to have a fault on the access, consider calling
@@ -899,7 +904,7 @@ SimpleCPU::tick()
#if FULL_SYSTEM
if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
- status() != IcacheMissComplete) {
+ status() != IcacheAccessComplete) {
int ipl = 0;
int summary = 0;
checkInterrupts = false;
@@ -968,11 +973,11 @@ SimpleCPU::tick()
#if SIMPLE_CPU_MEM_TIMING
CpuRequest *ifetch_req = new CpuRequest();
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req->setSize(sizeof(MachInst));
#endif
- ifetch_req->vaddr = cpuXC->readPC() & ~3;
- ifetch_req->time = curTick;
+ ifetch_req->setVaddr(cpuXC->readPC() & ~3);
+ ifetch_req->setTime(curTick);
/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
IFETCH_FLAGS(xc->regs.pc));
@@ -988,7 +993,7 @@ SimpleCPU::tick()
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
#endif
- ifetch_pkt->addr = ifetch_req->paddr;
+ ifetch_pkt->addr = ifetch_req->getPaddr();
sendIcacheRequest(ifetch_pkt);
#if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC
@@ -1089,7 +1094,7 @@ SimpleCPU::tick()
#endif // FULL_SYSTEM
}
else {
-#if THE_ISA != MIPS_ISA
+#if THE_ISA == ALPHA_ISA
// go to the next instruction
cpuXC->setPC(cpuXC->readNextPC());
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-04 23:56:27 +0000