summaryrefslogtreecommitdiff
path: root/cpu/simple/cpu.cc
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/simple/cpu.cc')
-rw-r--r--cpu/simple/cpu.cc41
1 files changed, 33 insertions, 8 deletions
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 0760f978c..b6823fb63 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -102,17 +102,42 @@ SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
{
}
-void SimpleCPU::CacheCompletionEvent::process()
+
+bool
+SimpleCPU::CpuPort::recvTiming(Packet &pkt)
{
- cpu->processCacheCompletion();
+ cpu->processResponse(pkt);
+ return true;
}
-const char *
-SimpleCPU::CacheCompletionEvent::description()
+Tick
+SimpleCPU::CpuPort::recvAtomic(Packet &pkt)
{
- return "SimpleCPU cache completion event";
+ panic("CPU doesn't expect callback!");
+ return curTick;
}
+void
+SimpleCPU::CpuPort::recvFunctional(Packet &pkt)
+{
+ panic("CPU doesn't expect callback!");
+}
+
+void
+SimpleCPU::CpuPort::recvStatusChange(Status status)
+{
+ cpu->recvStatusChange(status);
+}
+
+Packet *
+SimpleCPU::CpuPort::recvRetry()
+{
+ return cpu->processRetry();
+}
+
+
+
+
SimpleCPU::SimpleCPU(Params *p)
: BaseCPU(p), tickEvent(this, p->width), xc(NULL),
cacheCompletionEvent(this), dcachePort(this), icachePort(this)
@@ -697,9 +722,9 @@ SimpleCPU::sendDcacheRequest()
void
SimpleCPU::processResponse(Packet *response)
{
- // For what things is the CPU the consumer of the packet it sent out?
- // This may create a memory leak if that's the case and it's expected of the
- // SimpleCPU to delete its own packet.
+ // For what things is the CPU the consumer of the packet it sent
+ // out? This may create a memory leak if that's the case and it's
+ // expected of the SimpleCPU to delete its own packet.
pkt = response;
switch (status()) {