2 files changed, 32 insertions, 10 deletions

diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 9f4f821d4..2f1e8e1f1 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -47,6 +47,7 @@
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/full_cpu/smt.hh"
+#include "cpu/sampling_cpu/sampling_cpu.hh"
 #include "cpu/simple_cpu/simple_cpu.hh"
 #include "cpu/static_inst.hh"
 #include "mem/base_mem.hh"
@@ -179,11 +180,21 @@ SimpleCPU::~SimpleCPU()
 }
 
 void
-SimpleCPU::switchOut()
+SimpleCPU::switchOut(SamplingCPU *s)
 {
-    _status = SwitchedOut;
-    if (tickEvent.scheduled())
-        tickEvent.squash();
+    sampler = s;
+    if (status() == DcacheMissStall) {
+        DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n");
+        _status = DcacheMissSwitch;
+    }
+    else {
+        _status = SwitchedOut;
+
+        if (tickEvent.scheduled())
+            tickEvent.squash();
+
+        sampler->signalSwitched();
+    }
 }
 
 
@@ -203,8 +214,6 @@ SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
             tickEvent.schedule(curTick);
         }
     }
-
-    oldCPU->switchOut();
 }
 
 
@@ -631,6 +640,12 @@ SimpleCPU::processCacheCompletion()
         _status = Running;
         scheduleTickEvent(1);
         break;
+      case DcacheMissSwitch:
+        if (memReq->cmd.isRead()) {
+            curStaticInst->execute(this,traceData);
+        }
+        _status = SwitchedOut;
+        sampler->signalSwitched();
       case SwitchedOut:
         // If this CPU has been switched out due to sampling/warm-up,
         // ignore any further status changes (e.g., due to cache
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 8104d73a4..85bd1a74f 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -29,12 +29,13 @@
 #ifndef __SIMPLE_CPU_HH__
 #define __SIMPLE_CPU_HH__
 
-#include "cpu/base_cpu.hh"
-#include "sim/eventq.hh"
-#include "cpu/pc_event.hh"
 #include "base/statistics.hh"
+#include "cpu/base_cpu.hh"
 #include "cpu/exec_context.hh"
+#include "cpu/pc_event.hh"
+#include "cpu/sampling_cpu/sampling_cpu.hh"
 #include "cpu/static_inst.hh"
+#include "sim/eventq.hh"
 
 // forward declarations
 #ifdef FULL_SYSTEM
@@ -117,6 +118,7 @@ class SimpleCPU : public BaseCPU
         IcacheMissStall,
         IcacheMissComplete,
         DcacheMissStall,
+        DcacheMissSwitch,
         SwitchedOut
     };
 
@@ -163,7 +165,7 @@ class SimpleCPU : public BaseCPU
     // execution context
     ExecContext *xc;
 
-    void switchOut();
+    void switchOut(SamplingCPU *s);
     void takeOverFrom(BaseCPU *oldCPU);
 
 #ifdef FULL_SYSTEM
@@ -184,6 +186,11 @@ class SimpleCPU : public BaseCPU
     // Refcounted pointer to the one memory request.
     MemReqPtr memReq;
 
+    // Pointer to the sampler that is telling us to switchover.
+    // Used to signal the completion of the pipe drain and schedule
+    // the next switchover
+    SamplingCPU *sampler;
+
     StaticInstPtr<TheISA> curStaticInst;
 
     class CacheCompletionEvent : public Event