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-rw-r--r--cpu/static_inst.hh13
1 files changed, 11 insertions, 2 deletions
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 1065fa3d4..9a0425c8f 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -42,6 +42,7 @@
// forward declarations
class ExecContext;
class DynInst;
+class FastCPU;
class SimpleCPU;
class SymbolTable;
@@ -106,11 +107,13 @@ class StaticInstBase : public RefCounted
IsThreadSync, ///< Thread synchronization operation.
- IsSerializing, ///< Serializes pipeline: won't until all
+ IsSerializing, ///< Serializes pipeline: won't execute until all
/// older instructions have committed.
IsMemBarrier, ///< Is a memory barrier
IsWriteBarrier, ///< Is a write barrier
+ IsNonSpeculative, ///< Should not be executed speculatively
+
NumFlags
};
@@ -192,6 +195,7 @@ class StaticInstBase : public RefCounted
bool isSerializing() const { return flags[IsSerializing]; }
bool isMemBarrier() const { return flags[IsMemBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
+ bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
//@}
/// Operation class. Used to select appropriate function unit in issue.
@@ -310,6 +314,11 @@ class StaticInst : public StaticInstBase
virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
/**
+ * Execute this instruction under FastCPU model.
+ */
+ virtual Fault execute(FastCPU *xc, Trace::InstRecord *traceData) = 0;
+
+ /**
* Execute this instruction under detailed FullCPU model.
*/
virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0;