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-rw-r--r--cpu/trace/trace_cpu.cc4
-rw-r--r--cpu/trace/trace_cpu.hh2
2 files changed, 4 insertions, 2 deletions
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
index 1902d0be4..a0e4ef24c 100644
--- a/cpu/trace/trace_cpu.cc
+++ b/cpu/trace/trace_cpu.cc
@@ -108,10 +108,10 @@ TraceCPU::tick()
if (mainEventQueue.empty()) {
new SimExitEvent("Finshed Memory Trace");
} else {
- tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
+ tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
}
} else {
- tickEvent.schedule(max(curTick + 1, nextCycle));
+ tickEvent.schedule(max(curTick + cycles(1), nextCycle));
}
}
diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh
index cdac4bb4f..9b80e325d 100644
--- a/cpu/trace/trace_cpu.hh
+++ b/cpu/trace/trace_cpu.hh
@@ -105,6 +105,8 @@ class TraceCPU : public SimObject
MemInterface *dcache_interface,
MemTraceReader *data_trace);
+ inline Tick cycles(int numCycles) { return numCycles; }
+
/**
* Perform all the accesses for one cycle.
*/