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-rw-r--r--cpu/full_cpu/op_class.hh1
-rw-r--r--cpu/simple_cpu/simple_cpu.hh16
-rw-r--r--cpu/static_inst.cc2
-rw-r--r--cpu/static_inst.hh10
4 files changed, 15 insertions, 14 deletions
diff --git a/cpu/full_cpu/op_class.hh b/cpu/full_cpu/op_class.hh
index a14ccfaed..8e85e8d8a 100644
--- a/cpu/full_cpu/op_class.hh
+++ b/cpu/full_cpu/op_class.hh
@@ -51,6 +51,7 @@ enum OpClass {
FloatSqrtOp, /* floating point square root */
MemReadOp, /* memory read port */
MemWriteOp, /* memory write port */
+ IprAccessOp, /* Internal Processor Register read/write port */
InstPrefetchOp, /* instruction prefetch port (on I-cache) */
Num_OpClasses /* total functional unit classes */
};
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 0283545f4..c802a1c06 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -259,47 +259,47 @@ class SimpleCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
+ uint64_t readIntReg(const StaticInst<TheISA> *si, int idx)
{
return xc->readIntReg(si->srcRegIdx(idx));
}
- float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
+ float readFloatRegSingle(const StaticInst<TheISA> *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegSingle(reg_idx);
}
- double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
+ double readFloatRegDouble(const StaticInst<TheISA> *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegDouble(reg_idx);
}
- uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
+ uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegInt(reg_idx);
}
- void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
+ void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val)
{
xc->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
+ void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegSingle(reg_idx, val);
}
- void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
+ void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegDouble(reg_idx, val);
}
- void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
+ void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegInt(reg_idx, val);
diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc
index 7069d89ec..d522dbf5a 100644
--- a/cpu/static_inst.cc
+++ b/cpu/static_inst.cc
@@ -68,7 +68,7 @@ StaticInst<AlphaISA>::nullStaticInstPtr;
template <class ISA>
bool
-StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt)
+StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
{
if (isDirectCtrl()) {
tgt = branchTarget(pc);
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 25c98b12a..3ac88fd3d 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -294,13 +294,13 @@ class StaticInst : public StaticInstBase
* String representation of disassembly (lazily evaluated via
* disassemble()).
*/
- std::string *cachedDisassembly;
+ mutable std::string *cachedDisassembly;
/**
* Internal function to generate disassembly string.
*/
- virtual std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) = 0;
+ virtual std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
/// Constructor.
StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
@@ -347,7 +347,7 @@ class StaticInst : public StaticInstBase
* Return true if the instruction is a control transfer, and if so,
* return the target address as well.
*/
- bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
+ bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
/**
* Return string representation of disassembled instruction.
@@ -357,7 +357,7 @@ class StaticInst : public StaticInstBase
* should not be cached, this function should be overridden directly.
*/
virtual const std::string &disassemble(Addr pc,
- const SymbolTable *symtab = 0)
+ const SymbolTable *symtab = 0) const
{
if (!cachedDisassembly)
cachedDisassembly =