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-rw-r--r--cpu/cpu_exec_context.cc3
-rw-r--r--cpu/cpu_exec_context.hh36
-rw-r--r--cpu/exec_context.hh48
-rw-r--r--cpu/o3/alpha_cpu_impl.hh12
-rw-r--r--cpu/o3/alpha_dyn_inst.hh36
-rw-r--r--cpu/o3/cpu.cc47
-rw-r--r--cpu/o3/cpu.hh16
-rw-r--r--cpu/o3/regfile.hh80
-rw-r--r--cpu/ozone/cpu.hh36
-rw-r--r--cpu/simple/cpu.cc2
-rw-r--r--cpu/simple/cpu.hh39
11 files changed, 232 insertions, 123 deletions
diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index 2ad9571ce..79a4c00c6 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -276,8 +276,7 @@ CPUExecContext::copyArchRegs(ExecContext *xc)
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
- setFloatRegDouble(i, xc->readFloatRegDouble(i));
- setFloatRegInt(i, xc->readFloatRegInt(i));
+ setFloatRegBits(i, xc->readFloatRegBits(i));
}
// Copy misc. registers
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 509583d65..2a90e07d3 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -70,6 +70,8 @@ class CPUExecContext
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::FloatRegBits FloatRegBits;
public:
typedef ExecContext::Status Status;
@@ -374,19 +376,24 @@ class CPUExecContext
return regs.intRegFile[reg_idx];
}
- float readFloatRegSingle(int reg_idx)
+ FloatReg readFloatReg(int reg_idx, int width)
{
- return (float)regs.floatRegFile.d[reg_idx];
+ return regs.floatRegFile.readReg(reg_idx, width);
}
- double readFloatRegDouble(int reg_idx)
+ FloatReg readFloatReg(int reg_idx)
{
- return regs.floatRegFile.d[reg_idx];
+ return regs.floatRegFile.readReg(reg_idx);
}
- uint64_t readFloatRegInt(int reg_idx)
+ FloatRegBits readFloatRegBits(int reg_idx, int width)
{
- return regs.floatRegFile.q[reg_idx];
+ return regs.floatRegFile.readRegBits(reg_idx, width);
+ }
+
+ FloatRegBits readFloatRegBits(int reg_idx)
+ {
+ return regs.floatRegFile.readRegBits(reg_idx);
}
void setIntReg(int reg_idx, uint64_t val)
@@ -394,19 +401,24 @@ class CPUExecContext
regs.intRegFile[reg_idx] = val;
}
- void setFloatRegSingle(int reg_idx, float val)
+ void setFloatReg(int reg_idx, FloatReg val, int width)
+ {
+ regs.floatRegFile.setReg(reg_idx, val, width);
+ }
+
+ void setFloatReg(int reg_idx, FloatReg val)
{
- regs.floatRegFile.d[reg_idx] = (double)val;
+ regs.floatRegFile.setReg(reg_idx, val);
}
- void setFloatRegDouble(int reg_idx, double val)
+ void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
- regs.floatRegFile.d[reg_idx] = val;
+ regs.floatRegFile.setRegBits(reg_idx, val, width);
}
- void setFloatRegInt(int reg_idx, uint64_t val)
+ void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- regs.floatRegFile.q[reg_idx] = val;
+ regs.floatRegFile.setRegBits(reg_idx, val);
}
uint64_t readPC()
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index d102757e6..2fdb19c73 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -54,6 +54,8 @@ class ExecContext
typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::IntReg IntReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
public:
@@ -165,19 +167,23 @@ class ExecContext
//
virtual uint64_t readIntReg(int reg_idx) = 0;
- virtual float readFloatRegSingle(int reg_idx) = 0;
+ virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
- virtual double readFloatRegDouble(int reg_idx) = 0;
+ virtual FloatReg readFloatReg(int reg_idx) = 0;
- virtual uint64_t readFloatRegInt(int reg_idx) = 0;
+ virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
+
+ virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, uint64_t val) = 0;
- virtual void setFloatRegSingle(int reg_idx, float val) = 0;
+ virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
+
+ virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
- virtual void setFloatRegDouble(int reg_idx, double val) = 0;
+ virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
- virtual void setFloatRegInt(int reg_idx, uint64_t val) = 0;
+ virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
virtual uint64_t readPC() = 0;
@@ -333,26 +339,32 @@ class ProxyExecContext : public ExecContext
uint64_t readIntReg(int reg_idx)
{ return actualXC->readIntReg(reg_idx); }
- float readFloatRegSingle(int reg_idx)
- { return actualXC->readFloatRegSingle(reg_idx); }
+ FloatReg readFloatReg(int reg_idx, int width)
+ { return actualXC->readFloatReg(reg_idx, width); }
- double readFloatRegDouble(int reg_idx)
- { return actualXC->readFloatRegDouble(reg_idx); }
+ FloatReg readFloatReg(int reg_idx)
+ { return actualXC->readFloatReg(reg_idx); }
- uint64_t readFloatRegInt(int reg_idx)
- { return actualXC->readFloatRegInt(reg_idx); }
+ FloatRegBits readFloatRegBits(int reg_idx, int width)
+ { return actualXC->readFloatRegBits(reg_idx, width); }
+
+ FloatRegBits readFloatRegBits(int reg_idx)
+ { return actualXC->readFloatRegBits(reg_idx); }
void setIntReg(int reg_idx, uint64_t val)
{ actualXC->setIntReg(reg_idx, val); }
- void setFloatRegSingle(int reg_idx, float val)
- { actualXC->setFloatRegSingle(reg_idx, val); }
+ void setFloatReg(int reg_idx, FloatReg val, int width)
+ { actualXC->setFloatReg(reg_idx, val, width); }
+
+ void setFloatReg(int reg_idx, FloatReg val)
+ { actualXC->setFloatReg(reg_idx, val); }
- void setFloatRegDouble(int reg_idx, double val)
- { actualXC->setFloatRegDouble(reg_idx, val); }
+ void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
+ { actualXC->setFloatRegBits(reg_idx, val, width); }
- void setFloatRegInt(int reg_idx, uint64_t val)
- { actualXC->setFloatRegInt(reg_idx, val); }
+ void setFloatRegBits(int reg_idx, FloatRegBits val)
+ { actualXC->setFloatRegBits(reg_idx, val); }
uint64_t readPC() { return actualXC->readPC(); }
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 9f1fa24f6..7c4c2b969 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -175,10 +175,8 @@ AlphaFullCPU<Impl>::copyToXC()
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
- this->cpuXC->setFloatRegDouble(i,
- this->regFile.readFloatRegDouble(renamed_reg));
- this->cpuXC->setFloatRegInt(i,
- this->regFile.readFloatRegInt(renamed_reg));
+ this->cpuXC->setFloatRegBits(i,
+ this->regFile.readFloatRegBits(renamed_reg));
}
this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag,
@@ -223,10 +221,8 @@ AlphaFullCPU<Impl>::copyFromXC()
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
- this->regFile.setFloatRegDouble(renamed_reg,
- this->cpuXC->readFloatRegDouble(i));
- this->regFile.setFloatRegInt(renamed_reg,
- this->cpuXC->readFloatRegInt(i));
+ this->regFile.setFloatRegBits(renamed_reg,
+ this->cpuXC->readFloatRegBits(i));
}
// Then loop through the misc registers.
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index e7f7d3a57..5b8a05e5c 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -152,19 +152,24 @@ class AlphaDynInst : public BaseDynInst<Impl>
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
- float readFloatRegSingle(const StaticInst *si, int idx)
+ FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{
- return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
+ return this->cpu->readFloatReg(_srcRegIdx[idx], width);
}
- double readFloatRegDouble(const StaticInst *si, int idx)
+ FloatReg readFloatReg(const StaticInst *si, int idx)
{
- return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
+ return this->cpu->readFloatReg(_srcRegIdx[idx]);
}
- uint64_t readFloatRegInt(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{
- return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
+ return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
+ }
+
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ {
+ return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
}
/** @todo: Make results into arrays so they can handle multiple dest
@@ -176,21 +181,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
this->instResult.integer = val;
}
- void setFloatRegSingle(const StaticInst *si, int idx, float val)
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
- this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
+ this->cpu->setFloatReg(_destRegIdx[idx], val, width);
this->instResult.fp = val;
}
- void setFloatRegDouble(const StaticInst *si, int idx, double val)
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
- this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
+ this->cpu->setFloatReg(_destRegIdx[idx], val);
this->instResult.dbl = val;
}
- void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+ void setFloatRegBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
+ {
+ this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
+ this->instResult.integer = val;
+ }
+
+ void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
- this->cpu->setFloatRegInt(_destRegIdx[idx], val);
+ this->cpu->setFloatRegBits(_destRegIdx[idx], val);
this->instResult.integer = val;
}
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index 62d68bb33..a268dbc23 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -258,8 +258,7 @@ FullO3CPU<Impl>::init()
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i)
{
- regFile.floatRegFile[i].d = src_xc->readFloatRegDouble(i);
- regFile.floatRegFile[i].q = src_xc->readFloatRegInt(i);
+ regFile.floatRegFile.setRegBits(i, src_xc->readRegBits(i))
}
/*
// Then loop through the misc registers.
@@ -348,24 +347,31 @@ FullO3CPU<Impl>::readIntReg(int reg_idx)
}
template <class Impl>
-float
-FullO3CPU<Impl>::readFloatRegSingle(int reg_idx)
+FloatReg
+FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
{
- return regFile.readFloatRegSingle(reg_idx);
+ return regFile.readFloatReg(reg_idx, width);
}
template <class Impl>
-double
-FullO3CPU<Impl>::readFloatRegDouble(int reg_idx)
+FloatReg
+FullO3CPU<Impl>::readFloatReg(int reg_idx)
{
- return regFile.readFloatRegDouble(reg_idx);
+ return regFile.readFloatReg(reg_idx);
}
template <class Impl>
-uint64_t
-FullO3CPU<Impl>::readFloatRegInt(int reg_idx)
+FloatRegBits
+FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
+{
+ return regFile.readFloatRegBits(reg_idx, width);
+}
+
+template <class Impl>
+FloatRegBits
+FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
{
- return regFile.readFloatRegInt(reg_idx);
+ return regFile.readFloatRegBits(reg_idx);
}
template <class Impl>
@@ -377,23 +383,30 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
template <class Impl>
void
-FullO3CPU<Impl>::setFloatRegSingle(int reg_idx, float val)
+FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
+{
+ regFile.setFloatReg(reg_idx, val, width);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
- regFile.setFloatRegSingle(reg_idx, val);
+ regFile.setFloatReg(reg_idx, val);
}
template <class Impl>
void
-FullO3CPU<Impl>::setFloatRegDouble(int reg_idx, double val)
+FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
- regFile.setFloatRegDouble(reg_idx, val);
+ regFile.setFloatRegBits(reg_idx, val, width);
}
template <class Impl>
void
-FullO3CPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val)
+FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
- regFile.setFloatRegInt(reg_idx, val);
+ regFile.setFloatRegBits(reg_idx, val);
}
template <class Impl>
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 6577e46e4..f7c80e8a1 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -170,19 +170,23 @@ class FullO3CPU : public BaseFullCPU
//
uint64_t readIntReg(int reg_idx);
- float readFloatRegSingle(int reg_idx);
+ FloatReg readFloatReg(int reg_idx);
- double readFloatRegDouble(int reg_idx);
+ FloatReg readFloatReg(int reg_idx, int width);
- uint64_t readFloatRegInt(int reg_idx);
+ FloatRegBits readFloatRegBits(int reg_idx);
+
+ FloatRegBits readFloatRegBits(int reg_idx, int width);
void setIntReg(int reg_idx, uint64_t val);
- void setFloatRegSingle(int reg_idx, float val);
+ void setFloatReg(int reg_idx, FloatReg val, int width);
+
+ void setFloatReg(int reg_idx, FloatReg val, int width);
- void setFloatRegDouble(int reg_idx, double val);
+ void setFloatRegBits(int reg_idx, FloatRegBits val);
- void setFloatRegInt(int reg_idx, uint64_t val);
+ void setFloatRegBits(int reg_idx, FloatRegBits val);
uint64_t readPC();
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 1e6e10f29..a5cfa8f3c 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -89,43 +89,64 @@ class PhysRegFile
return intRegFile[reg_idx];
}
- float readFloatRegSingle(PhysRegIndex reg_idx)
+ FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Access to float register %i as single, has "
- "data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d);
+ FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
- return (float)floatRegFile[reg_idx].d;
+ DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
+ "data %8.8d\n", int(reg_idx), (double)floatReg);
+
+ return floatReg;
}
- double readFloatRegDouble(PhysRegIndex reg_idx)
+ FloatReg readFloatReg(PhysRegIndex reg_idx)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Access to float register %i as double, has "
- " data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d);
+ FloatReg floatReg = floatRegFile.readReg(reg_idx);
+
+ DPRINTF(IEW, "RegFile: Access to float register %i, has "
+ "data %8.8d\n", int(reg_idx), (double)floatReg);
- return floatRegFile[reg_idx].d;
+ return floatReg;
}
- uint64_t readFloatRegInt(PhysRegIndex reg_idx)
+ FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Access to float register %i as int, has data "
- "%lli\n", int(reg_idx), floatRegFile[reg_idx].q);
+ FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);
+
+ DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, "
+ "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
+
+ return floatRegBits;
+ }
+
+ FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
+ {
+ // Remove the base Float reg dependency.
+ reg_idx = reg_idx - numPhysicalIntRegs;
+
+ assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+
+ FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
+
+ DPRINTF(IEW, "RegFile: Access to float register %i as int, "
+ "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
- return floatRegFile[reg_idx].q;
+ return floatRegBits;
}
void setIntReg(PhysRegIndex reg_idx, uint64_t val)
@@ -138,33 +159,33 @@ class PhysRegFile
intRegFile[reg_idx] = val;
}
- void setFloatRegSingle(PhysRegIndex reg_idx, float val)
+ void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
- int(reg_idx), val);
+ DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
+ int(reg_idx), (double)val);
- floatRegFile[reg_idx].d = (double)val;
+ floatRegFile.setReg(reg_idx, val, width);
}
- void setFloatRegDouble(PhysRegIndex reg_idx, double val)
+ void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
- int(reg_idx), val);
+ DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
+ int(reg_idx), (double)val);
- floatRegFile[reg_idx].d = val;
+ floatRegFile.setReg(reg_idx, val);
}
- void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val)
+ void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
@@ -172,9 +193,22 @@ class PhysRegFile
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
- int(reg_idx), val);
+ int(reg_idx), (uint64_t)val);
+
+ floatRegFile.setRegBits(reg_idx, val, width);
+ }
+
+ void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
+ {
+ // Remove the base Float reg dependency.
+ reg_idx = reg_idx - numPhysicalIntRegs;
+
+ assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+
+ DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
+ int(reg_idx), (uint64_t)val);
- floatRegFile[reg_idx].q = val;
+ floatRegFile.setRegBits(reg_idx, val);
}
uint64_t readPC()
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index f5d84d656..fa849bb09 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -406,22 +406,28 @@ class OoOCPU : public BaseCPU
return xc->readIntReg(si->srcRegIdx(idx));
}
- float readFloatRegSingle(StaticInst *si, int idx)
+ FloatReg readFloatReg(StaticInst *si, int idx, width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return xc->readFloatRegSingle(reg_idx);
+ return xc->readFloatReg(reg_idx, width);
}
- double readFloatRegDouble(StaticInst *si, int idx)
+ FloatReg readFloatReg(StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return xc->readFloatRegDouble(reg_idx);
+ return xc->readFloatReg(reg_idx);
}
- uint64_t readFloatRegInt(StaticInst *si, int idx)
+ FloatRegBits readFloatRegBits(StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return xc->readFloatRegInt(reg_idx);
+ return xc->readFloatRegBits(reg_idx, width);
+ }
+
+ FloatRegBits readFloatRegBits(StaticInst *si, int idx)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return xc->readFloatRegBits(reg_idx);
}
void setIntReg(StaticInst *si, int idx, uint64_t val)
@@ -429,22 +435,28 @@ class OoOCPU : public BaseCPU
xc->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatRegSingle(StaticInst *si, int idx, float val)
+ void setFloatReg(StaticInst *si, int idx, FloatReg val, int width)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ xc->setFloatReg(reg_idx, val, width);
+ }
+
+ void setFloatReg(StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- xc->setFloatRegSingle(reg_idx, val);
+ xc->setFloatReg(reg_idx, val);
}
- void setFloatRegDouble(StaticInst *si, int idx, double val)
+ void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- xc->setFloatRegDouble(reg_idx, val);
+ xc->setFloatRegBits(reg_idx, val, width);
}
- void setFloatRegInt(StaticInst *si, int idx, uint64_t val)
+ void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- xc->setFloatRegInt(reg_idx, val);
+ xc->setFloatRegBits(reg_idx, val);
}
uint64_t readPC() { return PC; }
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 6e8764709..b335944e9 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -941,7 +941,7 @@ SimpleCPU::tick()
// maintain $r0 semantics
cpuXC->setIntReg(ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
- cpuXC->setFloatRegDouble(ZeroReg, 0.0);
+ cpuXC->setFloatReg(ZeroReg, 0.0);
#endif // ALPHA_ISA
if (status() == IcacheAccessComplete) {
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 21944a49f..c1cf7ce96 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -80,6 +80,8 @@ class SimpleCPU : public BaseCPU
protected:
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::FloatRegBits FloatRegBits;
class CpuPort : public Port
{
@@ -322,22 +324,28 @@ class SimpleCPU : public BaseCPU
return cpuXC->readIntReg(si->srcRegIdx(idx));
}
- float readFloatRegSingle(const StaticInst *si, int idx)
+ FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return cpuXC->readFloatRegSingle(reg_idx);
+ return cpuXC->readFloatReg(reg_idx, width);
}
- double readFloatRegDouble(const StaticInst *si, int idx)
+ FloatReg readFloatReg(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return cpuXC->readFloatRegDouble(reg_idx);
+ return cpuXC->readFloatReg(reg_idx);
}
- uint64_t readFloatRegInt(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return cpuXC->readFloatRegInt(reg_idx);
+ return cpuXC->readFloatRegBits(reg_idx, width);
+ }
+
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatRegBits(reg_idx);
}
void setIntReg(const StaticInst *si, int idx, uint64_t val)
@@ -345,22 +353,29 @@ class SimpleCPU : public BaseCPU
cpuXC->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatRegSingle(const StaticInst *si, int idx, float val)
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatReg(reg_idx, val, width);
+ }
+
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- cpuXC->setFloatRegSingle(reg_idx, val);
+ cpuXC->setFloatReg(reg_idx, val);
}
- void setFloatRegDouble(const StaticInst *si, int idx, double val)
+ void setFloatRegBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- cpuXC->setFloatRegDouble(reg_idx, val);
+ cpuXC->setFloatRegBits(reg_idx, val, width);
}
- void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+ void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- cpuXC->setFloatRegInt(reg_idx, val);
+ cpuXC->setFloatRegBits(reg_idx, val);
}
uint64_t readPC() { return cpuXC->readPC(); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 18:40:33 +0000