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-rw-r--r--cpu/simple_cpu/simple_cpu.hh2
-rw-r--r--cpu/static_inst.hh3
2 files changed, 2 insertions, 3 deletions
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 1c6b18d03..545c753f0 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -253,7 +253,7 @@ class SimpleCPU : public BaseCPU
// need to do this...
}
- void writeHint(Addr addr, int size)
+ void writeHint(Addr addr, int size, unsigned flags)
{
// need to do this...
}
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 3eeefb675..68c30df2f 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -72,8 +72,7 @@ class StaticInstBase : public RefCounted
/// unconditional branches, memory barriers) or both (e.g., an
/// FP/int conversion).
/// - If IsMemRef is set, then exactly one of IsLoad or IsStore
- /// will be set. Prefetches are marked as IsLoad, even if they
- /// prefetch exclusive copies.
+ /// will be set.
/// - If IsControl is set, then exactly one of IsDirectControl or
/// IsIndirect Control will be set, and exactly one of
/// IsCondControl or IsUncondControl will be set.