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-rw-r--r--cpu/base_cpu.cc5
-rw-r--r--cpu/base_cpu.hh14
-rw-r--r--cpu/memtest/memtest.cc2
-rw-r--r--cpu/memtest/memtest.hh3
-rw-r--r--cpu/simple_cpu/simple_cpu.cc6
-rw-r--r--cpu/simple_cpu/simple_cpu.hh6
-rw-r--r--cpu/trace/trace_cpu.cc4
-rw-r--r--cpu/trace/trace_cpu.hh2
8 files changed, 28 insertions, 14 deletions
diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index 01040015c..643a2b652 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -54,11 +54,12 @@ int maxThreadsPerCPU = 1;
extern void debug_break();
#ifdef FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
- : SimObject(p->name), frequency(p->freq), checkInterrupts(true),
+ : SimObject(p->name), cycleTime(p->cycleTime), checkInterrupts(true),
params(p), number_of_threads(p->numberOfThreads), system(p->system)
#else
BaseCPU::BaseCPU(Params *p)
- : SimObject(p->name), params(p), number_of_threads(p->numberOfThreads)
+ : SimObject(p->name), cycleTime(p->cycleTime), params(p),
+ number_of_threads(p->numberOfThreads)
#endif
{
DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh
index f346f4ec5..ea12460db 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base_cpu.hh
@@ -46,9 +46,17 @@ class ExecContext;
class BaseCPU : public SimObject
{
+ protected:
+ // CPU's clock period in terms of the number of ticks of curTime.
+ Tick cycleTime;
+
+ public:
+ inline Tick frequency() const { return Clock::Frequency / cycleTime; }
+ inline Tick cycles(int numCycles) const { return cycleTime * numCycles; }
+ inline Tick curCycle() const { return curTick / cycleTime; }
+
#ifdef FULL_SYSTEM
protected:
- Tick frequency;
uint64_t interrupts[NumInterruptLevels];
uint64_t intstatus;
@@ -67,8 +75,6 @@ class BaseCPU : public SimObject
bool check_interrupts() const { return intstatus != 0; }
uint64_t intr_status() const { return intstatus; }
-
- Tick getFreq() const { return frequency; }
#endif
protected:
@@ -100,7 +106,7 @@ class BaseCPU : public SimObject
Counter max_insts_all_threads;
Counter max_loads_any_thread;
Counter max_loads_all_threads;
- Tick freq;
+ Tick cycleTime;
bool functionTrace;
Tick functionTraceStart;
#ifdef FULL_SYSTEM
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 14b119880..86d03e162 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -225,7 +225,7 @@ void
MemTest::tick()
{
if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + 1);
+ tickEvent.schedule(curTick + cycles(1));
if (++noResponseCycles >= 500000) {
cerr << name() << ": deadlocked at cycle " << curTick << endl;
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 45b2d24e8..ed25cf374 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -60,6 +60,9 @@ class MemTest : public SimObject
// register statistics
virtual void regStats();
+
+ inline Tick cycles(int numCycles) const { return numCycles; }
+
// main simulation loop (one cycle)
void tick();
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 62bbb2fa8..06fee208d 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -806,7 +806,7 @@ SimpleCPU::tick()
status() == DcacheMissStall);
if (status() == Running && !tickEvent.scheduled())
- tickEvent.schedule(curTick + 1);
+ tickEvent.schedule(curTick + cycles(1));
}
@@ -831,6 +831,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
+ Param<int> cycle_time;
SimObjectParam<BaseMem *> icache;
SimObjectParam<BaseMem *> dcache;
@@ -862,6 +863,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
+ INIT_PARAM(cycle_time, "cpu cycle time"),
INIT_PARAM(icache, "L1 instruction cache object"),
INIT_PARAM(dcache, "L1 data cache object"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
@@ -887,7 +889,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
params->deferRegistration = defer_registration;
- params->freq = ticksPerSecond;
+ params->cycleTime = cycle_time;
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->icache_interface = (icache) ? icache->getInterface() : NULL;
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index f245a7bba..2056ff707 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -80,12 +80,12 @@ class SimpleCPU : public BaseCPU
TickEvent tickEvent;
/// Schedule tick event, regardless of its current state.
- void scheduleTickEvent(int delay)
+ void scheduleTickEvent(int numCycles)
{
if (tickEvent.squashed())
- tickEvent.reschedule(curTick + delay);
+ tickEvent.reschedule(curTick + cycles(numCycles));
else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + delay);
+ tickEvent.schedule(curTick + cycles(numCycles));
}
/// Unschedule tick event, regardless of its current state.
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
index 1902d0be4..a0e4ef24c 100644
--- a/cpu/trace/trace_cpu.cc
+++ b/cpu/trace/trace_cpu.cc
@@ -108,10 +108,10 @@ TraceCPU::tick()
if (mainEventQueue.empty()) {
new SimExitEvent("Finshed Memory Trace");
} else {
- tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
+ tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
}
} else {
- tickEvent.schedule(max(curTick + 1, nextCycle));
+ tickEvent.schedule(max(curTick + cycles(1), nextCycle));
}
}
diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh
index cdac4bb4f..9b80e325d 100644
--- a/cpu/trace/trace_cpu.hh
+++ b/cpu/trace/trace_cpu.hh
@@ -105,6 +105,8 @@ class TraceCPU : public SimObject
MemInterface *dcache_interface,
MemTraceReader *data_trace);
+ inline Tick cycles(int numCycles) { return numCycles; }
+
/**
* Perform all the accesses for one cycle.
*/