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-rw-r--r--cpu/exec_context.hh13
1 files changed, 6 insertions, 7 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index ddfc53684..4a2688f1c 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -218,7 +218,7 @@ class ExecContext
cregs = &req->xc->regs.miscRegs;
if (req->flags & UNCACHEABLE) {
- // Don't update result register (see machine.def)
+ // Don't update result register (see stq_c in isa_desc)
req->result = 2;
req->xc->storeCondFailures = 0;//Needed? [RGD]
} else {
@@ -239,12 +239,11 @@ class ExecContext
}
}
- // Need to clear any locked flags on other proccessors for this
- // address
- // Only do this for succsful Store Conditionals and all other
- // stores (WH64?)
- // Unsuccesful Store Conditionals would have returned above,
- // and wouldn't fall through
+ // Need to clear any locked flags on other proccessors for
+ // this address. Only do this for succsful Store Conditionals
+ // and all other stores (WH64?). Unsuccessful Store
+ // Conditionals would have returned above, and wouldn't fall
+ // through.
for (int i = 0; i < system->xcvec.size(); i++){
cregs = &system->xcvec[i]->regs.miscRegs;
if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {