5 files changed, 46 insertions, 18 deletions

diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index c6cff814d..fe88891d6 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -130,6 +130,13 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
 void
 BaseCPU::regStats()
 {
+    using namespace Statistics;
+
+    numCycles
+        .name(name() + ".numCycles")
+        .desc("number of cpu cycles simulated")
+        ;
+
     int size = execContexts.size();
     if (size > 1) {
         for (int i = 0; i < size; ++i) {
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh
index 0041ecc99..0b4a38b0e 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base_cpu.hh
@@ -31,10 +31,10 @@
 
 #include <vector>
 
+#include "base/statistics.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
-
-#include "targetarch/isa_traits.hh"	// for Addr
+#include "targetarch/isa_traits.hh"
 
 #ifdef FULL_SYSTEM
 class System;
@@ -147,11 +147,27 @@ class BaseCPU : public SimObject
      */
     virtual BranchPred *getBranchPred() { return NULL; };
 
+    virtual Counter totalInstructions() const { return 0; }
+
   private:
     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 
   public:
     static int numSimulatedCPUs() { return cpuList.size(); }
+    static Counter numSimulatedInstructions()
+    {
+        Counter total = 0;
+
+        int size = cpuList.size();
+        for (int i = 0; i < size; ++i)
+            total += cpuList[i]->totalInstructions();
+
+        return total;
+    }
+
+  public:
+    // Number of CPU cycles simulated
+    Statistics::Scalar<> numCycles;
 };
 
 #endif // __BASE_CPU_HH__
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 065140883..617c91e68 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -50,7 +50,6 @@
 #include "cpu/static_inst.hh"
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
-#include "sim/annotation.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
@@ -287,8 +286,6 @@ SimpleCPU::regStats()
         ;
 
     idleFraction = constant(1.0) - notIdleFraction;
-    numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
-    simInsts += numInsts;
 }
 
 void
@@ -581,7 +578,6 @@ SimpleCPU::post_interrupt(int int_num, int index)
     if (xc->status() == ExecContext::Suspended) {
                 DPRINTF(IPI,"Suspended Processor awoke\n");
         xc->activate();
-        Annotate::Resume(xc);
     }
 }
 #endif // FULL_SYSTEM
@@ -590,6 +586,8 @@ SimpleCPU::post_interrupt(int int_num, int index)
 void
 SimpleCPU::tick()
 {
+    numCycles++;
+
     traceData = NULL;
 
     Fault fault = No_Fault;
@@ -697,6 +695,7 @@ SimpleCPU::tick()
 
         // keep an instruction count
         numInst++;
+        numInsts++;
 
         // check for instruction-count-based events
         comInstEventQueue[0]->serviceEvents(numInst);
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 4977e6992..a04dcd057 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -34,7 +34,7 @@
 #include "base/loader/symtab.hh"
 #include "cpu/pc_event.hh"
 #include "base/statistics.hh"
-
+#include "cpu/exec_context.hh"
 
 // forward declarations
 #ifdef FULL_SYSTEM
@@ -46,6 +46,11 @@ class PhysicalMemory;
 
 class RemoteGDB;
 class GDBListener;
+
+#else
+
+class Process;
+
 #endif // FULL_SYSTEM
 
 class MemInterface;
@@ -204,7 +209,12 @@ class SimpleCPU : public BaseCPU
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;
-    Statistics::Formula numInsts;
+    Statistics::Scalar<> numInsts;
+
+    virtual Counter totalInstructions() const
+    {
+        return numInst - startNumInst;
+    }
 
     // number of simulated memory references
     Statistics::Scalar<> numMemRefs;
@@ -300,6 +310,4 @@ class SimpleCPU : public BaseCPU
     ExecContext *xcBase() { return xc; }
 };
 
-typedef SimpleCPU SimpleCPUExecContext;
-
 #endif // __SIMPLE_CPU_HH__
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 57208f8e6..1065fa3d4 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -42,9 +42,7 @@
 // forward declarations
 class ExecContext;
 class DynInst;
-typedef DynInst FullCPUExecContext;
 class SimpleCPU;
-typedef SimpleCPU SimpleCPUExecContext;
 class SymbolTable;
 
 namespace Trace {
@@ -249,7 +247,8 @@ class StaticInst : public StaticInstBase
      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
      * just the EA computation.
      */
-    virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
+    virtual const
+    StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -257,7 +256,8 @@ class StaticInst : public StaticInstBase
      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
      * just the memory access (not the EA computation).
      */
-    virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
+    virtual const
+    StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
 
     /// The binary machine instruction.
     const MachInst machInst;
@@ -307,14 +307,12 @@ class StaticInst : public StaticInstBase
     /**
      * Execute this instruction under SimpleCPU model.
      */
-    virtual Fault execute(SimpleCPUExecContext *xc,
-                          Trace::InstRecord *traceData) = 0;
+    virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
 
     /**
      * Execute this instruction under detailed FullCPU model.
      */
-    virtual Fault execute(FullCPUExecContext *xc,
-                          Trace::InstRecord *traceData) = 0;
+    virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0;
 
     /**
      * Return the target address for a PC-relative branch.