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-rw-r--r--cpu/base_dyn_inst.cc7
-rw-r--r--cpu/cpu_exec_context.cc66
-rw-r--r--cpu/cpu_exec_context.hh33
-rw-r--r--cpu/o3/alpha_cpu.hh2
-rw-r--r--cpu/o3/alpha_cpu_builder.cc4
-rw-r--r--cpu/o3/alpha_cpu_impl.hh23
-rw-r--r--cpu/o3/bpred_unit.hh2
-rw-r--r--cpu/o3/comm.hh2
-rw-r--r--cpu/o3/cpu.hh2
-rw-r--r--cpu/o3/regfile.hh8
-rw-r--r--cpu/ozone/cpu.hh2
-rw-r--r--cpu/ozone/cpu_impl.hh2
-rw-r--r--cpu/ozone/ea_list.cc2
-rw-r--r--cpu/ozone/ea_list.hh2
-rw-r--r--cpu/profile.hh2
-rw-r--r--cpu/simple/cpu.cc22
-rw-r--r--cpu/simple/cpu.hh2
-rw-r--r--cpu/static_inst.hh16
18 files changed, 122 insertions, 77 deletions
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index a40b4a1dd..bf7c35cad 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -36,7 +36,7 @@
#include "base/cprintf.hh"
#include "base/trace.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/faults.hh"
#include "cpu/exetrace.hh"
#include "mem/mem_req.hh"
@@ -45,6 +45,7 @@
#include "cpu/o3/alpha_cpu.hh"
using namespace std;
+using namespace TheISA;
#define NOHASH
#ifndef NOHASH
@@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars()
asid = 0;
// Initialize the fault to be unimplemented opcode.
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
++instcount;
@@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
break;
default:
- fault = MachineCheckFault;
+ fault = genMachineCheckFault();
break;
}
diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index 2fb3d5d53..ae428646d 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -36,12 +36,13 @@
#include "base/callback.hh"
#include "base/cprintf.hh"
#include "base/output.hh"
+#include "base/trace.hh"
#include "cpu/profile.hh"
#include "kern/kernel_stats.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-#include "targetarch/stacktrace.hh"
+#include "arch/stacktrace.hh"
#else
#include "sim/process.hh"
#endif
@@ -54,8 +55,9 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
FunctionalMemory *_mem)
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
- cpu_id(-1), mem(_mem), itb(_itb), dtb(_dtb), system(_sys),
- memctrl(_sys->memctrl), physmem(_sys->physmem), profile(NULL),
+ cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
+ dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
+ fnbin(kernelBinning->fnbin), profile(NULL), quiesceEvent(this),
func_exe_inst(0), storeCondFailures(0)
{
proxy = new ProxyExecContext<CPUExecContext>(this);
@@ -80,8 +82,8 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
Process *_process, int _asid)
: _status(ExecContext::Unallocated),
- cpu(_cpu), thread_num(_thread_num), cpu_id(-1),
- process(_process), mem(process->getMemory()), asid(_asid),
+ cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
+ lastSuspend(0), process(_process), mem(process->getMemory()), asid(_asid),
func_exe_inst(0), storeCondFailures(0)
{
memset(&regs, 0, sizeof(RegFile));
@@ -117,7 +119,23 @@ void
CPUExecContext::dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
- profile->dump(proxy, *os);
+}
+
+ExecContext::EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
+ : Event(&mainEventQueue), xc(_xc)
+{
+}
+
+void
+ExecContext::EndQuiesceEvent::process()
+{
+ xc->activate();
+}
+
+const char*
+ExecContext::EndQuiesceEvent::description()
+{
+ return "End Quiesce Event.";
}
#endif
@@ -153,6 +171,14 @@ CPUExecContext::serialize(ostream &os)
// thread_num and cpu_id are deterministic from the config
SERIALIZE_SCALAR(func_exe_inst);
SERIALIZE_SCALAR(inst);
+
+#if FULL_SYSTEM
+ Tick quiesceEndTick = 0;
+ if (quiesceEvent.scheduled())
+ quiesceEndTick = quiesceEvent.when();
+ SERIALIZE_SCALAR(quiesceEndTick);
+
+#endif
}
@@ -164,6 +190,13 @@ CPUExecContext::unserialize(Checkpoint *cp, const std::string &section)
// thread_num and cpu_id are deterministic from the config
UNSERIALIZE_SCALAR(func_exe_inst);
UNSERIALIZE_SCALAR(inst);
+
+#if FULL_SYSTEM
+ Tick quiesceEndTick;
+ UNSERIALIZE_SCALAR(quiesceEndTick);
+ if (quiesceEndTick)
+ quiesceEvent.schedule(quiesceEndTick);
+#endif
}
@@ -173,6 +206,8 @@ CPUExecContext::activate(int delay)
if (status() == ExecContext::Active)
return;
+ lastActivate = curTick;
+
_status = ExecContext::Active;
cpu->activateContext(thread_num, delay);
}
@@ -183,6 +218,9 @@ CPUExecContext::suspend()
if (status() == ExecContext::Suspended)
return;
+ lastActivate = curTick;
+ lastSuspend = curTick;
+/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->check_interrupts()) {
@@ -190,7 +228,7 @@ CPUExecContext::suspend()
return;
}
#endif
-
+*/
_status = ExecContext::Suspended;
cpu->suspendContext(thread_num);
}
@@ -248,15 +286,3 @@ CPUExecContext::copyArchRegs(ExecContext *xc)
setNextPC(xc->readNextPC());
}
-void
-CPUExecContext::trap(Fault fault)
-{
- //TheISA::trap(fault); //One possible way to do it...
-
- /** @todo: Going to hack it for now. Do a true fixup later. */
-#if FULL_SYSTEM
- ev5_trap(fault);
-#else
- fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
-#endif
-}
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 1ae24582d..a40253d4b 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -35,6 +35,7 @@
#include "mem/functional/functional.hh"
#include "mem/mem_req.hh"
#include "sim/byteswap.hh"
+#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
@@ -46,7 +47,7 @@ class BaseCPU;
#if FULL_SYSTEM
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
+#include "arch/tlb.hh"
class FunctionProfile;
class ProfileNode;
@@ -114,6 +115,9 @@ class CPUExecContext
// it belongs. For full-system mode, this is the system CPU ID.
int cpu_id;
+ Tick lastActivate;
+ Tick lastSuspend;
+
#if FULL_SYSTEM
FunctionalMemory *mem;
AlphaITB *itb;
@@ -131,6 +135,22 @@ class CPUExecContext
Addr profilePC;
void dumpFuncProfile();
+ /** Event for timing out quiesce instruction */
+ struct EndQuiesceEvent : public Event
+ {
+ /** A pointer to the execution context that is quiesced */
+ ExecContext *xc;
+
+ EndQuiesceEvent(ExecContext *_xc);
+
+ /** Event process to occur at interrupt*/
+ virtual void process();
+
+ /** Event description */
+ virtual const char *description();
+ };
+ EndQuiesceEvent quiesceEvent;
+
#else
Process *process;
@@ -447,18 +467,9 @@ class CPUExecContext
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
- void ev5_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif
- /** Meant to be more generic trap function to be
- * called when an instruction faults.
- * @param fault The fault generated by executing the instruction.
- * @todo How to do this properly so it's dependent upon ISA only?
- */
-
- void trap(Fault fault);
-
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 75a4d72c2..531f6aa45 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -275,7 +275,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
#endif
- return this->mem->write(req, (T)::htog(data));
+ return this->mem->write(req, (T)htog(data));
}
template <class T>
diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 7e687ad2b..6025b8ef2 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -49,8 +49,8 @@
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/tlb.hh"
+#include "arch/vtophys.hh"
#else // !FULL_SYSTEM
#include "mem/functional/functional.hh"
#endif // FULL_SYSTEM
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 271b542ab..33e363d4f 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -260,7 +260,7 @@ Fault
AlphaFullCPU<Impl>::hwrei()
{
if (!inPalMode())
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
@@ -305,24 +305,25 @@ template <class Impl>
void
AlphaFullCPU<Impl>::trap(Fault fault)
{
- // Keep in mind that a trap may be initiated by fetch if there's a TLB
+/* // Keep in mind that a trap may be initiated by fetch if there's a TLB
// miss
uint64_t PC = this->commit.readCommitPC();
- DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
- this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
+ DPRINTF(Fault, "Fault %s\n", fault->name());
+ this->recordEvent(csprintf("Fault %s", fault->name()));
-// kernelStats.fault(fault);
+ //kernelStats.fault(fault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
// exception restart address - Get the commit PC
- if (fault != InterruptFault || !inPalMode(PC))
+ if (!fault->isA<InterruptFault>() || !inPalMode(PC))
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
- if (fault == PalFault || fault == ArithmeticFault /* ||
- fault == InterruptFault && !PC_PAL(regs.pc) */) {
+ if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>())
+ // || fault == InterruptFault && !PC_PAL(regs.pc)
+ {
// traps... skip faulting instruction
AlphaISA::MiscReg ipr_exc_addr =
this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
@@ -334,8 +335,8 @@ AlphaFullCPU<Impl>::trap(Fault fault)
swapPALShadow(true);
this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
- AlphaISA::fault_addr(fault) );
- this->regFile.setNextPC(PC + sizeof(MachInst));
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect());
+ this->regFile.setNextPC(PC + sizeof(MachInst));*/
}
template <class Impl>
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 0a77b83dc..2725684f7 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -30,7 +30,7 @@
#define __BPRED_UNIT_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh
index e4de1d304..c74c77ddf 100644
--- a/cpu/o3/comm.hh
+++ b/cpu/o3/comm.hh
@@ -31,7 +31,7 @@
#include <vector>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
#include "sim/host.hh"
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 45e21db7f..8f29a25fb 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -50,7 +50,7 @@
#include "sim/process.hh"
#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
+#include "arch/ev5.hh"
using namespace EV5;
#endif
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 1bc7159f6..03ad2da46 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -31,14 +31,14 @@
// @todo: Destructor
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
+#include "arch/ev5.hh"
#include "kern/kernel_stats.hh"
using namespace EV5;
@@ -236,7 +236,7 @@ class PhysRegFile
#if FULL_SYSTEM
private:
// This is ISA specifc stuff; remove it eventually once ISAImpl is used
- IntReg palregs[NumIntRegs]; // PAL shadow registers
+// IntReg palregs[NumIntRegs]; // PAL shadow registers
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 667e2b3f8..f5d84d656 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -517,7 +517,7 @@ class OoOCPU : public BaseCPU
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
- void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
+ void trap(Fault fault) { fault->invoke(xc); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh
index 009a81b98..e7ed3cfe0 100644
--- a/cpu/ozone/cpu_impl.hh
+++ b/cpu/ozone/cpu_impl.hh
@@ -29,7 +29,7 @@
#ifndef __CPU_OOO_CPU_OOO_IMPL_HH__
#define __CPU_OOO_CPU_OOO_IMPL_HH__
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
template <class Impl>
class OoOCPU;
diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc
index 80cf80fb8..6114a0ca1 100644
--- a/cpu/ozone/ea_list.cc
+++ b/cpu/ozone/ea_list.cc
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ooo_cpu/ea_list.hh"
diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh
index def7e67d5..c0eee4bb8 100644
--- a/cpu/ozone/ea_list.hh
+++ b/cpu/ozone/ea_list.hh
@@ -32,7 +32,7 @@
#include <list>
#include <utility>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
/**
diff --git a/cpu/profile.hh b/cpu/profile.hh
index 18061f9bf..1eb012a27 100644
--- a/cpu/profile.hh
+++ b/cpu/profile.hh
@@ -33,7 +33,7 @@
#include "cpu/static_inst.hh"
#include "sim/host.hh"
-#include "targetarch/stacktrace.hh"
+#include "arch/stacktrace.hh"
class ProfileNode
{
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 7c60b242f..38b43fef5 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -68,9 +68,9 @@
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/stacktrace.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/tlb.hh"
+#include "arch/stacktrace.hh"
+#include "arch/vtophys.hh"
#else // !FULL_SYSTEM
#include "mem/functional/functional.hh"
#endif // FULL_SYSTEM
@@ -350,12 +350,12 @@ SimpleCPU::copySrcTranslate(Addr src)
// translate to physical address
Fault fault = cpuXC->translateDataReadReq(memReq);
- assert(fault != AlignmentFault);
-
if (fault == NoFault) {
cpuXC->copySrcAddr = src;
cpuXC->copySrcPhysAddr = memReq->paddr + offset;
} else {
+ assert(!fault->isAlignmentFault());
+
cpuXC->copySrcAddr = 0;
cpuXC->copySrcPhysAddr = 0;
}
@@ -385,8 +385,6 @@ SimpleCPU::copy(Addr dest)
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(memReq);
- assert(fault != AlignmentFault);
-
if (fault == NoFault) {
Addr dest_addr = memReq->paddr + offset;
// Need to read straight from memory since we have more than 8 bytes.
@@ -405,6 +403,9 @@ SimpleCPU::copy(Addr dest)
dcacheInterface->access(memReq);
}
}
+ else
+ assert(!fault->isAlignmentFault());
+
return fault;
}
@@ -690,7 +691,8 @@ SimpleCPU::tick()
if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) {
cpuXC->setMiscReg(IPR_ISR, summary);
cpuXC->setMiscReg(IPR_INTID, ipl);
- cpuXC->ev5_trap(InterruptFault);
+
+ Fault(new InterruptFault)->invoke(xcProxy);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
@@ -764,7 +766,7 @@ SimpleCPU::tick()
// decode the instruction
inst = gtoh(inst);
- curStaticInst = StaticInst::decode(inst);
+ curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC()));
traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
cpuXC->readPC());
@@ -815,7 +817,7 @@ SimpleCPU::tick()
if (fault != NoFault) {
#if FULL_SYSTEM
- cpuXC->ev5_trap(fault);
+ fault->invoke(xcProxy);
#else // !FULL_SYSTEM
fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC());
#endif // FULL_SYSTEM
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 1441a8fcd..4ab9a1c3e 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -350,7 +350,7 @@ class SimpleCPU : public BaseCPU
int readIntrFlag() { return cpuXC->readIntrFlag(); }
void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
bool inPalMode() { return cpuXC->inPalMode(); }
- void ev5_trap(Fault fault) { cpuXC->ev5_trap(fault); }
+ void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
#else
void syscall() { cpuXC->syscall(); }
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index a0287a2de..20116554e 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -109,6 +109,8 @@ class StaticInstBase : public RefCounted
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
+ IsCondDelaySlot,///< Conditional Delay-Slot Instruction
+
IsThreadSync, ///< Thread synchronization operation.
IsSerializing, ///< Serializes pipeline: won't execute until all
@@ -229,6 +231,8 @@ class StaticInst : public StaticInstBase
/// Binary machine instruction type.
typedef TheISA::MachInst MachInst;
+ /// Binary extended machine instruction type.
+ typedef TheISA::ExtMachInst ExtMachInst;
/// Logical register index type.
typedef TheISA::RegIndex RegIndex;
@@ -270,7 +274,7 @@ class StaticInst : public StaticInstBase
StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.
- const MachInst machInst;
+ const ExtMachInst machInst;
protected:
@@ -300,7 +304,7 @@ class StaticInst : public StaticInstBase
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
/// Constructor.
- StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
+ StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
: StaticInstBase(__opClass),
machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
{
@@ -370,7 +374,7 @@ class StaticInst : public StaticInstBase
/// Decoded instruction cache type.
/// For now we're using a generic hash_map; this seems to work
/// pretty well.
- typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache;
+ typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
/// A cache of decoded instruction objects.
static DecodeCache decodeCache;
@@ -385,7 +389,7 @@ class StaticInst : public StaticInstBase
/// @param mach_inst The binary instruction to decode.
/// @retval A pointer to the corresponding StaticInst object.
//This is defined as inline below.
- static StaticInstPtr decode(MachInst mach_inst);
+ static StaticInstPtr decode(ExtMachInst mach_inst);
};
typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
@@ -416,7 +420,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst>
/// Construct directly from machine instruction.
/// Calls StaticInst::decode().
- StaticInstPtr(TheISA::MachInst mach_inst)
+ StaticInstPtr(TheISA::ExtMachInst mach_inst)
: RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
{
}
@@ -429,7 +433,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst>
};
inline StaticInstPtr
-StaticInst::decode(StaticInst::MachInst mach_inst)
+StaticInst::decode(StaticInst::ExtMachInst mach_inst)
{
#ifdef DECODE_CACHE_HASH_STATS
// Simple stats on decode hash_map. Turns out the default
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 00:09:56 +0000