5 files changed, 10 insertions, 10 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 6f38a6960..2bde053b2 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -34,7 +34,7 @@
 #include "mem/mem_req.hh"
 #include "sim/host.hh"
 #include "sim/serialize.hh"
-#include "targetarch/byte_swap.hh"
+#include "sim/byteswap.hh"
 
 // forward declaration: see functional_memory.hh
 class FunctionalMemory;
@@ -269,7 +269,7 @@ class ExecContext
 
         Fault error;
         error = mem->read(req, data);
-        data = gtoh(data);
+        data = LittleEndianGuest::gtoh(data);
         return error;
     }
 
@@ -319,7 +319,7 @@ class ExecContext
         }
 
 #endif
-        return mem->write(req, (T)htog(data));
+        return mem->write(req, (T)LittleEndianGuest::htog(data));
     }
 
     virtual bool misspeculating();
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index cba57d189..164da4968 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -220,7 +220,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
         Fault error;
         error = this->mem->read(req, data);
-        data = gtoh(data);
+        data = LittleEndianGuest::gtoh(data);
         return error;
     }
 
@@ -277,7 +277,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
 #endif
 
-        return this->mem->write(req, (T)htog(data));
+        return this->mem->write(req, (T)LittleEndianGuest::htog(data));
     }
 
     template <class T>
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 2a764740b..3b16975a9 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -42,9 +42,6 @@
 #if FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/isa_traits.hh"
-//#include "arch/alpha/ev5.hh"
-
-//using namespace EV5;
 #endif
 
 template <class Impl>
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index c943fd36a..1a8411cc1 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -30,7 +30,7 @@
 #define OPCODE(X)                       (X >> 26) & 0x3f
 
 
-#include "arch/alpha/byte_swap.hh"
+#include "sim/byteswap.hh"
 #include "cpu/exetrace.hh"
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
@@ -535,7 +535,7 @@ SimpleFetch<Impl>::fetch()
             assert(offset <= cacheBlkSize - instSize);
 
             // Get the instruction from the array of the cache line.
-            inst = gtoh(*reinterpret_cast<MachInst *>
+            inst = LittleEndianGuest::gtoh(*reinterpret_cast<MachInst *>
                         (&cacheData[offset]));
 
             // Create a new DynInst from the instruction fetched.
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index a7f4fa499..70217f0bb 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -54,6 +54,7 @@
 #include "kern/kernel_stats.hh"
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
+#include "sim/byteswap.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
@@ -74,6 +75,8 @@
 #endif // FULL_SYSTEM
 
 using namespace std;
+//The SimpleCPU does alpha only
+using namespace LittleEndianGuest;
 
 
 SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)