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-rw-r--r--cpu/base_dyn_inst.cc7
-rw-r--r--cpu/exec_context.cc4
-rw-r--r--cpu/exec_context.hh4
-rw-r--r--cpu/o3/alpha_cpu.hh2
-rw-r--r--cpu/o3/alpha_cpu_builder.cc4
-rw-r--r--cpu/o3/alpha_cpu_impl.hh16
-rw-r--r--cpu/o3/bpred_unit.hh2
-rw-r--r--cpu/o3/comm.hh2
-rw-r--r--cpu/o3/cpu.hh2
-rw-r--r--cpu/o3/regfile.hh6
-rw-r--r--cpu/ozone/cpu_impl.hh2
-rw-r--r--cpu/ozone/ea_list.cc2
-rw-r--r--cpu/ozone/ea_list.hh2
-rw-r--r--cpu/profile.hh2
-rw-r--r--cpu/simple/cpu.cc14
-rw-r--r--cpu/simple/cpu.hh2
-rw-r--r--cpu/static_inst.hh2
17 files changed, 39 insertions, 36 deletions
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 86314bef1..5905cdad2 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -36,7 +36,7 @@
#include "base/cprintf.hh"
#include "base/trace.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/faults.hh"
#include "cpu/exetrace.hh"
#include "mem/mem_req.hh"
@@ -45,6 +45,7 @@
#include "cpu/o3/alpha_cpu.hh"
using namespace std;
+using namespace TheISA;
#define NOHASH
#ifndef NOHASH
@@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars()
asid = 0;
// Initialize the fault to be unimplemented opcode.
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
++instcount;
@@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
break;
default:
- fault = MachineCheckFault;
+ fault = genMachineCheckFault();
break;
}
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 9bed3ba47..7e8b81e18 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -40,7 +40,7 @@
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-#include "targetarch/stacktrace.hh"
+#include "arch/stacktrace.hh"
#else
#include "sim/process.hh"
#endif
@@ -227,7 +227,7 @@ ExecContext::trap(Fault fault)
/** @todo: Going to hack it for now. Do a true fixup later. */
#if FULL_SYSTEM
- ev5_trap(fault);
+ fault->ev5_trap(this);
#else
fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
#endif
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 88b12c301..7ab8c589e 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -46,7 +46,7 @@ class BaseCPU;
#if FULL_SYSTEM
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
+#include "arch/tlb.hh"
class FunctionProfile;
class ProfileNode;
@@ -427,7 +427,7 @@ class ExecContext
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
- void ev5_trap(Fault fault);
+ void ev5_temp_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 47ea532a6..38c00a3a9 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -276,7 +276,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
#endif
- return this->mem->write(req, (T)::htog(data));
+ return this->mem->write(req, (T)htog(data));
}
template <class T>
diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 3547fb1b5..95d2f8f37 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -50,8 +50,8 @@
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/tlb.hh"
+#include "arch/vtophys.hh"
#else // !FULL_SYSTEM
#include "mem/functional/functional.hh"
#endif // FULL_SYSTEM
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index bd4e34914..daa61bb1c 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -257,7 +257,7 @@ Fault
AlphaFullCPU<Impl>::hwrei()
{
if (!inPalMode())
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
@@ -306,19 +306,19 @@ AlphaFullCPU<Impl>::trap(Fault fault)
// miss
uint64_t PC = this->commit.readCommitPC();
- DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
- this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
+ DPRINTF(Fault, "Fault %s\n", fault->name());
+ this->recordEvent(csprintf("Fault %s", fault->name()));
-// kernelStats.fault(fault);
+ //kernelStats.fault(fault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
// exception restart address - Get the commit PC
- if (fault != InterruptFault || !inPalMode(PC))
+ if (!fault->isA<InterruptFault>() || !inPalMode(PC))
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
- if (fault == PalFault || fault == ArithmeticFault /* ||
+ if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
AlphaISA::MiscReg ipr_exc_addr =
@@ -331,7 +331,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
swapPALShadow(true);
this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
- AlphaISA::fault_addr(fault) );
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect());
this->regFile.setNextPC(PC + sizeof(MachInst));
}
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 0a77b83dc..2725684f7 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -30,7 +30,7 @@
#define __BPRED_UNIT_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh
index e4de1d304..c74c77ddf 100644
--- a/cpu/o3/comm.hh
+++ b/cpu/o3/comm.hh
@@ -31,7 +31,7 @@
#include <vector>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
#include "sim/host.hh"
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 09d9c3d66..02908887e 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -50,7 +50,7 @@
#include "sim/process.hh"
#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
+#include "arch/ev5.hh"
using namespace EV5;
#endif
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 1bc7159f6..691a75382 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -31,14 +31,14 @@
// @todo: Destructor
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
+#include "arch/ev5.hh"
#include "kern/kernel_stats.hh"
using namespace EV5;
diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh
index 009a81b98..e7ed3cfe0 100644
--- a/cpu/ozone/cpu_impl.hh
+++ b/cpu/ozone/cpu_impl.hh
@@ -29,7 +29,7 @@
#ifndef __CPU_OOO_CPU_OOO_IMPL_HH__
#define __CPU_OOO_CPU_OOO_IMPL_HH__
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
template <class Impl>
class OoOCPU;
diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc
index 80cf80fb8..6114a0ca1 100644
--- a/cpu/ozone/ea_list.cc
+++ b/cpu/ozone/ea_list.cc
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ooo_cpu/ea_list.hh"
diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh
index def7e67d5..c0eee4bb8 100644
--- a/cpu/ozone/ea_list.hh
+++ b/cpu/ozone/ea_list.hh
@@ -32,7 +32,7 @@
#include <list>
#include <utility>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
/**
diff --git a/cpu/profile.hh b/cpu/profile.hh
index 18061f9bf..1eb012a27 100644
--- a/cpu/profile.hh
+++ b/cpu/profile.hh
@@ -33,7 +33,7 @@
#include "cpu/static_inst.hh"
#include "sim/host.hh"
-#include "targetarch/stacktrace.hh"
+#include "arch/stacktrace.hh"
class ProfileNode
{
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index dd2d53c17..d826c589e 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -67,9 +67,9 @@
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/stacktrace.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/tlb.hh"
+#include "arch/stacktrace.hh"
+#include "arch/vtophys.hh"
#else // !FULL_SYSTEM
#include "mem/functional/functional.hh"
#endif // FULL_SYSTEM
@@ -347,7 +347,7 @@ SimpleCPU::copySrcTranslate(Addr src)
// translate to physical address
Fault fault = xc->translateDataReadReq(memReq);
- assert(fault != AlignmentFault);
+ assert(!fault->isAlignmentFault());
if (fault == NoFault) {
xc->copySrcAddr = src;
@@ -382,7 +382,7 @@ SimpleCPU::copy(Addr dest)
// translate to physical address
Fault fault = xc->translateDataWriteReq(memReq);
- assert(fault != AlignmentFault);
+ assert(!fault->isAlignmentFault());
if (fault == NoFault) {
Addr dest_addr = memReq->paddr + offset;
@@ -687,7 +687,7 @@ SimpleCPU::tick()
if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) {
xc->setMiscReg(IPR_ISR, summary);
xc->setMiscReg(IPR_INTID, ipl);
- xc->ev5_trap(InterruptFault);
+ (new InterruptFault)->ev5_trap(xc);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
xc->readMiscReg(IPR_IPLR), ipl, summary);
@@ -811,7 +811,7 @@ SimpleCPU::tick()
if (fault != NoFault) {
#if FULL_SYSTEM
- xc->ev5_trap(fault);
+ fault->ev5_trap(xc);
#else // !FULL_SYSTEM
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
#endif // FULL_SYSTEM
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 3bc905be1..243172821 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -347,7 +347,7 @@ class SimpleCPU : public BaseCPU
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
- void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
+ void ev5_trap(Fault fault) { fault->ev5_trap(xc); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index a0287a2de..5566f2f6d 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -109,6 +109,8 @@ class StaticInstBase : public RefCounted
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
+ IsCondDelaySlot,///< Conditional Delay-Slot Instruction
+
IsThreadSync, ///< Thread synchronization operation.
IsSerializing, ///< Serializes pipeline: won't execute until all
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-19 20:32:17 +0000