diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/base_cpu.hh | 3 | ||||
| -rw-r--r-- | cpu/exec_context.hh | 13 | ||||
| -rw-r--r-- | cpu/exetrace.hh | 13 | ||||
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 4 |
4 files changed, 9 insertions, 24 deletions
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh index 5946ced2f..e5d9df6de 100644 --- a/cpu/base_cpu.hh +++ b/cpu/base_cpu.hh @@ -120,9 +120,6 @@ class BaseCPU : public SimObject System *system; #endif - virtual bool filterThisInstructionPrefetch(int thread_number, - short asid, Addr prefetchTarget) const { return true; } - /** * Return pointer to CPU's branch predictor (NULL if none). * @return Branch predictor pointer. diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index ddfc53684..4a2688f1c 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -218,7 +218,7 @@ class ExecContext cregs = &req->xc->regs.miscRegs; if (req->flags & UNCACHEABLE) { - // Don't update result register (see machine.def) + // Don't update result register (see stq_c in isa_desc) req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { @@ -239,12 +239,11 @@ class ExecContext } } - // Need to clear any locked flags on other proccessors for this - // address - // Only do this for succsful Store Conditionals and all other - // stores (WH64?) - // Unsuccesful Store Conditionals would have returned above, - // and wouldn't fall through + // Need to clear any locked flags on other proccessors for + // this address. Only do this for succsful Store Conditionals + // and all other stores (WH64?). Unsuccessful Store + // Conditionals would have returned above, and wouldn't fall + // through. for (int i = 0; i < system->xcvec.size(); i++){ cregs = &system->xcvec[i]->regs.miscRegs; if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh index 8e2ea6221..d05dbe0cd 100644 --- a/cpu/exetrace.hh +++ b/cpu/exetrace.hh @@ -43,19 +43,6 @@ class BaseCPU; namespace Trace { -#if 0 - static const FlagVec ALL = ULL(0x1); - static const FlagVec FULL = ULL(0x2); - static const FlagVec SYMBOLS = ULL(0x4); - static const FlagVec EXTENDED = ULL(0x8); - static const FlagVec BRANCH_TAKEN = ULL(0x10); - static const FlagVec BRANCH_NOTTAKEN = ULL(0x20); - static const FlagVec CALLPAL = ULL(0x40); - static const FlagVec SPECULATIVE = ULL(0x100); - static const FlagVec OMIT_COUNT = ULL(0x200); - static const FlagVec INCLUDE_THREAD_NUM = ULL(0x400); -#endif - class InstRecord : public Record { protected: diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 28009b7f0..20790bfb6 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -192,8 +192,10 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process, memReq = new MemReq(); memReq->xc = xc; memReq->asid = 0; + memReq->data = new uint8_t[64]; numInst = 0; + numLoad = 0; last_idle = 0; lastIcacheStall = 0; lastDcacheStall = 0; @@ -406,7 +408,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) if (fault == No_Fault && dcacheInterface) { memReq->cmd = Write; - memReq->data = (uint8_t *)&data; + memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; memReq->flags &= ~UNCACHEABLE; |