4 files changed, 46 insertions, 15 deletions

diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 0b45d2b9d..8ea5798ea 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -345,13 +345,13 @@ SimpleCPU::copySrcTranslate(Addr src)
     int offset = src & (blk_size - 1);
 
     // Make sure block doesn't span page
-    if (no_warn && (src & (~8191)) != ((src + blk_size) & (~8191)) &&
+    if (no_warn &&
+        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
         (src >> 40) != 0xfffffc) {
         warn("Copied block source spans pages %x.", src);
         no_warn = false;
     }
 
-
     memReq->reset(src & ~(blk_size - 1), blk_size);
 
     // translate to physical address
@@ -381,7 +381,8 @@ SimpleCPU::copy(Addr dest)
     int offset = dest & (blk_size - 1);
 
     // Make sure block doesn't span page
-    if (no_warn && (dest & (~8191)) != ((dest + blk_size) & (~8191)) &&
+    if (no_warn &&
+        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
         (dest >> 40) != 0xfffffc) {
         no_warn = false;
         warn("Copied block destination spans pages %x. ", dest);
@@ -400,6 +401,15 @@ SimpleCPU::copy(Addr dest)
         xc->mem->read(memReq, data);
         memReq->paddr = dest_addr;
         xc->mem->write(memReq, data);
+        if (dcacheInterface) {
+            memReq->cmd = Copy;
+            memReq->completionEvent = NULL;
+            memReq->paddr = xc->copySrcPhysAddr;
+            memReq->dest = dest_addr;
+            memReq->size = 64;
+            memReq->time = curTick;
+            dcacheInterface->access(memReq);
+        }
     }
     return fault;
 }
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 451c801ee..d0000dc5b 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -249,8 +249,7 @@ class SimpleCPU : public BaseCPU
     Fault read(Addr addr, T &data, unsigned flags);
 
     template <class T>
-    Fault write(T data, Addr addr, unsigned flags,
-                        uint64_t *res);
+    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
     void prefetch(Addr addr, unsigned flags)
     {
diff --git a/cpu/trace/opt_cpu.cc b/cpu/trace/opt_cpu.cc
index 291525c1d..df4197e26 100644
--- a/cpu/trace/opt_cpu.cc
+++ b/cpu/trace/opt_cpu.cc
@@ -52,7 +52,13 @@ OptCPU::OptCPU(const string &name,
       numBlks(cache_size/block_size), assoc(_assoc), numSets(numBlks/assoc),
       setMask(numSets - 1)
 {
-    int log_block_size = (int)(log((double) block_size)/log(2.0));
+    int log_block_size = 0;
+    int tmp_block_size = block_size;
+    while (tmp_block_size > 1) {
+        ++log_block_size;
+        tmp_block_size = tmp_block_size >> 1;
+    }
+    assert(1<<log_block_size == block_size);
     MemReqPtr req;
     trace->getNextReq(req);
     refInfo.resize(numSets);
@@ -124,7 +130,7 @@ OptCPU::processSet(int set)
     for (int start = assoc/2; start >= 0; --start) {
         heapify(set,start);
     }
-    verifyHeap(set,0);
+    //verifyHeap(set,0);
 
     for (; i < refInfo[set].size(); ++i) {
         RefIndex cache_index = lookupValue(refInfo[set][i].addr);
@@ -134,8 +140,11 @@ OptCPU::processSet(int set)
             // replace from cacheHeap[0]
             // mark replaced block as absent
             setValue(refInfo[set][cacheHeap[0]].addr, -1);
+            setValue(refInfo[set][i].addr, 0);
             cacheHeap[0] = i;
             heapify(set, 0);
+            // Make sure its in the cache
+            assert(lookupValue(refInfo[set][i].addr) != -1);
         } else {
             // hit
             hits++;
@@ -143,9 +152,11 @@ OptCPU::processSet(int set)
                    refInfo[set][i].addr);
             assert(refInfo[set][cacheHeap[cache_index]].nextRefTime == i);
             assert(heapLeft(cache_index) >= assoc);
+
+            cacheHeap[cache_index] = i;
+            processRankIncrease(set, cache_index);
+            assert(lookupValue(refInfo[set][i].addr) != -1);
         }
-        cacheHeap[cache_index] = i;
-        processRankIncrease(set, cache_index);
     }
 }
 void
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
index e19509fec..b69793a4b 100644
--- a/cpu/trace/trace_cpu.cc
+++ b/cpu/trace/trace_cpu.cc
@@ -75,9 +75,14 @@ TraceCPU::tick()
                 icacheInterface->squash(nextReq->asid);
             } else {
                 ++instReqs;
-                nextReq->completionEvent =
-                    new TraceCompleteEvent(nextReq, this);
-                icacheInterface->access(nextReq);
+                if (icacheInterface->doEvents()) {
+                    nextReq->completionEvent =
+                        new TraceCompleteEvent(nextReq, this);
+                    icacheInterface->access(nextReq);
+                } else {
+                    icacheInterface->access(nextReq);
+                    completeRequest(nextReq);
+                }
             }
         } else {
             if (dcacheInterface->isBlocked())
@@ -85,9 +90,15 @@ TraceCPU::tick()
 
             ++dataReqs;
             nextReq->time = curTick;
-            nextReq->completionEvent =
-                new TraceCompleteEvent(nextReq, this);
-            dcacheInterface->access(nextReq);
+            if (dcacheInterface->doEvents()) {
+                nextReq->completionEvent =
+                    new TraceCompleteEvent(nextReq, this);
+                dcacheInterface->access(nextReq);
+            } else {
+                dcacheInterface->access(nextReq);
+                completeRequest(nextReq);
+            }
+
         }
         nextCycle = dataTrace->getNextReq(nextReq);
     }