diff options
Diffstat (limited to 'cpu')
40 files changed, 393 insertions, 398 deletions
diff --git a/cpu/base.cc b/cpu/base.cc index 8b94b8533..5a7ecf152 100644 --- a/cpu/base.cc +++ b/cpu/base.cc @@ -250,7 +250,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) } #if FULL_SYSTEM - for (int i = 0; i < NumInterruptLevels; ++i) + for (int i = 0; i < TheISA::NumInterruptLevels; ++i) interrupts[i] = oldCPU->interrupts[i]; intstatus = oldCPU->intstatus; @@ -285,7 +285,7 @@ BaseCPU::post_interrupt(int int_num, int index) { DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); - if (int_num < 0 || int_num >= NumInterruptLevels) + if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) panic("int_num out of bounds\n"); if (index < 0 || index >= sizeof(uint64_t) * 8) @@ -301,7 +301,7 @@ BaseCPU::clear_interrupt(int int_num, int index) { DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); - if (int_num < 0 || int_num >= NumInterruptLevels) + if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) panic("int_num out of bounds\n"); if (index < 0 || index >= sizeof(uint64_t) * 8) @@ -325,14 +325,14 @@ BaseCPU::clear_interrupts() void BaseCPU::serialize(std::ostream &os) { - SERIALIZE_ARRAY(interrupts, NumInterruptLevels); + SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); SERIALIZE_SCALAR(intstatus); } void BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); + UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); UNSERIALIZE_SCALAR(intstatus); } diff --git a/cpu/base.hh b/cpu/base.hh index 2bd1210d8..d5764d495 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -58,7 +58,7 @@ class BaseCPU : public SimObject #if FULL_SYSTEM protected: - uint64_t interrupts[NumInterruptLevels]; + uint64_t interrupts[TheISA::NumInterruptLevels]; uint64_t intstatus; public: @@ -68,7 +68,7 @@ class BaseCPU : public SimObject bool checkInterrupts; bool check_interrupt(int int_num) const { - if (int_num > NumInterruptLevels) + if (int_num > TheISA::NumInterruptLevels) panic("int_num out of bounds\n"); return interrupts[int_num] != 0; @@ -140,6 +140,8 @@ class BaseCPU : public SimObject virtual void startup(); virtual void regStats(); + virtual void activateWhenReady(int tid) {}; + void registerExecContexts(); /// Prepare for another CPU to take over execution. When it is diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index d921bd148..86314bef1 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -79,7 +79,7 @@ BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC, } template <class Impl> -BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst) +BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst) : staticInst(_staticInst), traceData(NULL) { initVars(); @@ -113,7 +113,7 @@ BaseDynInst<Impl>::initVars() asid = 0; // Initialize the fault to be unimplemented opcode. - fault = Unimplemented_Opcode_Fault; + fault = UnimplementedOpcodeFault; ++instcount; @@ -142,12 +142,12 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) req->asid = asid; // Prefetches never cause faults. - fault = No_Fault; + fault = NoFault; // note this is a local, not BaseDynInst::fault Fault trans_fault = xc->translateDataReadReq(req); - if (trans_fault == No_Fault && !(req->flags & UNCACHEABLE)) { + if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) { // It's a valid address to cacheable space. Record key MemReq // parameters so we can generate another one just like it for // the timing access without calling translate() again (which @@ -188,7 +188,7 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags) fault = xc->translateDataWriteReq(req); - if (fault == No_Fault && !(req->flags & UNCACHEABLE)) { + if (fault == NoFault && !(req->flags & UNCACHEABLE)) { // Record key MemReq parameters so we can generate another one // just like it for the timing access without calling translate() // again (which might mess up the TLB). @@ -217,7 +217,7 @@ BaseDynInst<Impl>::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(req); - if (fault == No_Fault) { + if (fault == NoFault) { xc->copySrcAddr = src; xc->copySrcPhysAddr = req->paddr; } else { @@ -243,7 +243,7 @@ BaseDynInst<Impl>::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(req); - if (fault == No_Fault) { + if (fault == NoFault) { Addr dest_addr = req->paddr; // Need to read straight from memory since we have more than 8 bytes. req->paddr = xc->copySrcPhysAddr; @@ -292,7 +292,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) #if 0 panic("unaligned access. Cycle = %n", curTick); #endif - return No_Fault; + return NoFault; } MemReqPtr req = new MemReq(addr, thread, nbytes); @@ -303,7 +303,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) case Write: fault = spec_mem->write(req, (uint8_t *)p); - if (fault != No_Fault) + if (fault != NoFault) break; specMemWrite = true; @@ -325,7 +325,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) break; default: - fault = Machine_Check_Fault; + fault = MachineCheckFault; break; } diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh index d29257a52..e94c44151 100644 --- a/cpu/base_dyn_inst.hh +++ b/cpu/base_dyn_inst.hh @@ -51,7 +51,6 @@ */ // Forward declaration. -template <class ISA> class StaticInstPtr; template <class Impl> @@ -61,25 +60,20 @@ class BaseDynInst : public FastAlloc, public RefCounted // Typedef for the CPU. typedef typename Impl::FullCPU FullCPU; - //Typedef to get the ISA. - typedef typename Impl::ISA ISA; - /// Binary machine instruction type. - typedef typename ISA::MachInst MachInst; - /// Memory address type. - typedef typename ISA::Addr Addr; + typedef TheISA::MachInst MachInst; /// Logical register index type. - typedef typename ISA::RegIndex RegIndex; + typedef TheISA::RegIndex RegIndex; /// Integer register index type. - typedef typename ISA::IntReg IntReg; + typedef TheISA::IntReg IntReg; enum { - MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs - MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs + MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs + MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs }; /** The static inst used by this dyn inst. */ - StaticInstPtr<ISA> staticInst; + StaticInstPtr staticInst; //////////////////////////////////////////// // @@ -214,7 +208,7 @@ class BaseDynInst : public FastAlloc, public RefCounted FullCPU *cpu); /** BaseDynInst constructor given a static inst pointer. */ - BaseDynInst(StaticInstPtr<ISA> &_staticInst); + BaseDynInst(StaticInstPtr &_staticInst); /** BaseDynInst destructor. */ ~BaseDynInst(); @@ -472,7 +466,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) req->paddr = req->vaddr; #endif - if (fault == No_Fault) { + if (fault == NoFault) { fault = cpu->read(req, data, lqIdx); } else { // Return a fixed value to keep simulation deterministic even @@ -520,14 +514,14 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) req->paddr = req->vaddr; #endif - if (fault == No_Fault) { + if (fault == NoFault) { fault = cpu->write(req, data, sqIdx); } if (res) { // always return some result to keep misspeculated paths // (which will ignore faults) deterministic - *res = (fault == No_Fault) ? req->result : 0; + *res = (fault == NoFault) ? req->result : 0; } return fault; diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 846be831a..3e0d77254 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -35,6 +35,7 @@ #include "sim/host.hh" #include "sim/serialize.hh" #include "arch/isa_traits.hh" +//#include "arch/isa_registers.hh" #include "sim/byteswap.hh" // forward declaration: see functional_memory.hh @@ -66,6 +67,10 @@ namespace Kernel { class Binning; class Statistics; } class ExecContext { + protected: + typedef TheISA::RegFile RegFile; + typedef TheISA::MachInst MachInst; + typedef TheISA::MiscRegFile MiscRegFile; public: enum Status { @@ -80,7 +85,7 @@ class ExecContext Active, /// Temporarily inactive. Entered while waiting for - /// synchronization, etc. + /// initialization,synchronization, etc. Suspended, /// Permanently shut down. Entered when target executes @@ -95,6 +100,8 @@ class ExecContext public: Status status() const { return _status; } + void setStatus(Status newStatus) { _status = newStatus; } + /// Set the status to Active. Optional delay indicates number of /// cycles to wait before beginning execution. void activate(int delay = 1); @@ -240,7 +247,7 @@ class ExecContext // put the asid in the upper 16 bits of the paddr req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; - return No_Fault; + return NoFault; } Fault translateInstReq(MemReqPtr &req) { @@ -301,7 +308,7 @@ class ExecContext << "on cpu " << req->xc->cpu_id << std::endl; } - return No_Fault; + return NoFault; } else req->xc->storeCondFailures = 0; } @@ -431,15 +438,15 @@ class ExecContext void trap(Fault fault); #if !FULL_SYSTEM - IntReg getSyscallArg(int i) + TheISA::IntReg getSyscallArg(int i) { - return regs.intRegFile[ArgumentReg0 + i]; + return regs.intRegFile[TheISA::ArgumentReg0 + i]; } // used to shift args for indirect syscall - void setSyscallArg(int i, IntReg val) + void setSyscallArg(int i, TheISA::IntReg val) { - regs.intRegFile[ArgumentReg0 + i] = val; + regs.intRegFile[TheISA::ArgumentReg0 + i] = val; } void setSyscallReturn(SyscallReturn return_value) @@ -451,11 +458,11 @@ class ExecContext if (return_value.successful()) { // no error regs.intRegFile[RegA3] = 0; - regs.intRegFile[ReturnValueReg] = return_value.value(); + regs.intRegFile[TheISA::ReturnValueReg] = return_value.value(); } else { // got an error, return details - regs.intRegFile[RegA3] = (IntReg) -1; - regs.intRegFile[ReturnValueReg] = -return_value.value(); + regs.intRegFile[RegA3] = (TheISA::IntReg) -1; + regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value(); } } diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh index 48d8966d8..67d042ec8 100644 --- a/cpu/exetrace.hh +++ b/cpu/exetrace.hh @@ -46,13 +46,14 @@ namespace Trace { class InstRecord : public Record { protected: + typedef TheISA::IntRegFile IntRegFile; // The following fields are initialized by the constructor and // thus guaranteed to be valid. BaseCPU *cpu; // need to make this ref-counted so it doesn't go away before we // dump the record - StaticInstPtr<TheISA> staticInst; + StaticInstPtr staticInst; Addr PC; bool misspeculating; unsigned thread; @@ -92,7 +93,7 @@ class InstRecord : public Record public: InstRecord(Tick _cycle, BaseCPU *_cpu, - const StaticInstPtr<TheISA> &_staticInst, + const StaticInstPtr &_staticInst, Addr _pc, bool spec, int _thread) : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc), misspeculating(spec), thread(_thread) @@ -169,7 +170,7 @@ InstRecord::setRegs(const IntRegFile ®s) inline InstRecord * getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu, - const StaticInstPtr<TheISA> staticInst, + const StaticInstPtr staticInst, Addr pc, int thread = 0) { if (DTRACE(InstExec) && diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc index 27f790fac..5a4024587 100644 --- a/cpu/memtest/memtest.cc +++ b/cpu/memtest/memtest.cc @@ -44,6 +44,7 @@ #include "sim/stats.hh" using namespace std; +using namespace TheISA; int TESTER_ALLOCATOR=0; diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh index a97ce455c..97433e542 100644 --- a/cpu/o3/2bit_local_pred.hh +++ b/cpu/o3/2bit_local_pred.hh @@ -30,7 +30,7 @@ #define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/o3/sat_counter.hh" class DefaultBP diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 1e1a72af0..b35bcf9e3 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -39,8 +39,9 @@ template <class Impl> class AlphaFullCPU : public FullO3CPU<Impl> { + protected: + typedef TheISA::IntReg IntReg; public: - typedef typename Impl::ISA AlphaISA; typedef typename Impl::Params Params; public: @@ -87,7 +88,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> // put the asid in the upper 16 bits of the paddr req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; - return No_Fault; + return NoFault; } Fault translateInstReq(MemReqPtr &req) @@ -259,7 +260,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> << "on cpu " << this->cpu_id << std::endl; } - return No_Fault; + return NoFault; } else req->xc->storeCondFailures = 0; } diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 3b16975a9..7ec1ba663 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -280,9 +280,9 @@ AlphaFullCPU<Impl>::hwrei() uint64_t *ipr = getIpr(); if (!inPalMode()) - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; - setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); + this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); // kernelStats.hwrei(); @@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::hwrei() this->checkInterrupts = true; // FIXME: XXX check for interrupts? XXX - return No_Fault; + return NoFault; } template <class Impl> @@ -329,22 +329,22 @@ AlphaFullCPU<Impl>::trap(Fault fault) // miss uint64_t PC = this->commit.readCommitPC(); - DPRINTF(Fault, "Fault %s\n", FaultName(fault)); - this->recordEvent(csprintf("Fault %s", FaultName(fault))); + DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name"); + this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name")); // kernelStats.fault(fault); - if (fault == Arithmetic_Fault) + if (fault == ArithmeticFault) panic("Arithmetic traps are unimplemented!"); - typename AlphaISA::InternalProcReg *ipr = getIpr(); + AlphaISA::InternalProcReg *ipr = getIpr(); // exception restart address - Get the commit PC - if (fault != Interrupt_Fault || !inPalMode(PC)) + if (fault != InterruptFault || !inPalMode(PC)) ipr[AlphaISA::IPR_EXC_ADDR] = PC; - if (fault == Pal_Fault || fault == Arithmetic_Fault /* || - fault == Interrupt_Fault && !PC_PAL(regs.pc) */) { + if (fault == PalFault || fault == ArithmeticFault /* || + fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction ipr[AlphaISA::IPR_EXC_ADDR] += 4; } @@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault) swapPALShadow(true); this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + - AlphaISA::fault_addr[fault] ); + AlphaISA::fault_addr(fault) ); this->regFile.setNextPC(PC + sizeof(MachInst)); } diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index bb90bf21a..f282c287c 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -48,21 +48,16 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Typedef for the CPU. */ typedef typename Impl::FullCPU FullCPU; - /** Typedef to get the ISA. */ - typedef typename Impl::ISA ISA; - /** Binary machine instruction type. */ - typedef typename ISA::MachInst MachInst; - /** Memory address type. */ - typedef typename ISA::Addr Addr; + typedef TheISA::MachInst MachInst; /** Logical register index type. */ - typedef typename ISA::RegIndex RegIndex; + typedef TheISA::RegIndex RegIndex; /** Integer register index type. */ - typedef typename ISA::IntReg IntReg; + typedef TheISA::IntReg IntReg; enum { - MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs - MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs + MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs + MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs }; public: @@ -71,7 +66,7 @@ class AlphaDynInst : public BaseDynInst<Impl> FullCPU *cpu); /** BaseDynInst constructor given a static inst pointer. */ - AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst); + AlphaDynInst(StaticInstPtr &_staticInst); /** Executes the instruction.*/ Fault execute() @@ -130,22 +125,22 @@ class AlphaDynInst : public BaseDynInst<Impl> // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst<ISA> *si, int idx) + uint64_t readIntReg(const StaticInst *si, int idx) { return this->cpu->readIntReg(_srcRegIdx[idx]); } - float readFloatRegSingle(const StaticInst<ISA> *si, int idx) + float readFloatRegSingle(const StaticInst *si, int idx) { return this->cpu->readFloatRegSingle(_srcRegIdx[idx]); } - double readFloatRegDouble(const StaticInst<ISA> *si, int idx) + double readFloatRegDouble(const StaticInst *si, int idx) { return this->cpu->readFloatRegDouble(_srcRegIdx[idx]); } - uint64_t readFloatRegInt(const StaticInst<ISA> *si, int idx) + uint64_t readFloatRegInt(const StaticInst *si, int idx) { return this->cpu->readFloatRegInt(_srcRegIdx[idx]); } @@ -153,25 +148,25 @@ class AlphaDynInst : public BaseDynInst<Impl> /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst<ISA> *si, int idx, uint64_t val) + void setIntReg(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); this->instResult.integer = val; } - void setFloatRegSingle(const StaticInst<ISA> *si, int idx, float val) + void setFloatRegSingle(const StaticInst *si, int idx, float val) { this->cpu->setFloatRegSingle(_destRegIdx[idx], val); this->instResult.fp = val; } - void setFloatRegDouble(const StaticInst<ISA> *si, int idx, double val) + void setFloatRegDouble(const StaticInst *si, int idx, double val) { this->cpu->setFloatRegDouble(_destRegIdx[idx], val); this->instResult.dbl = val; } - void setFloatRegInt(const StaticInst<ISA> *si, int idx, uint64_t val) + void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) { this->cpu->setFloatRegInt(_destRegIdx[idx], val); this->instResult.integer = val; diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh index d1ebb812d..eebe7675a 100644 --- a/cpu/o3/alpha_dyn_inst_impl.hh +++ b/cpu/o3/alpha_dyn_inst_impl.hh @@ -50,7 +50,7 @@ AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, } template <class Impl> -AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst) +AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst) : BaseDynInst<Impl>(_staticInst) { // Make sure to have the renamed register entries set to the same diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh index 6c1156041..5e39fcb37 100644 --- a/cpu/o3/alpha_impl.hh +++ b/cpu/o3/alpha_impl.hh @@ -51,11 +51,8 @@ class AlphaFullCPU; */ struct AlphaSimpleImpl { - /** The ISA to be used. */ - typedef AlphaISA ISA; - /** The type of MachInst. */ - typedef ISA::MachInst MachInst; + typedef TheISA::MachInst MachInst; /** The CPU policy to be used (ie fetch, decode, etc.). */ typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol; diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh index 9cb2e0490..8d16a0cdf 100644 --- a/cpu/o3/bpred_unit_impl.hh +++ b/cpu/o3/bpred_unit_impl.hh @@ -98,6 +98,8 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC) // Save off record of branch stuff so the RAS can be fixed // up once it's done. + using TheISA::MachInst; + bool pred_taken = false; Addr target; diff --git a/cpu/o3/btb.cc b/cpu/o3/btb.cc index 7671e61e2..2d39c3856 100644 --- a/cpu/o3/btb.cc +++ b/cpu/o3/btb.cc @@ -30,6 +30,8 @@ #include "base/trace.hh" #include "cpu/o3/btb.hh" +using namespace TheISA; + DefaultBTB::DefaultBTB(unsigned _numEntries, unsigned _tagBits, unsigned _instShiftAmt) diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh index a4ddfecb4..77bdc32ea 100644 --- a/cpu/o3/btb.hh +++ b/cpu/o3/btb.hh @@ -30,7 +30,7 @@ #define __CPU_O3_CPU_BTB_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" class DefaultBTB { diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh index 6ddc8d6b9..580c1a316 100644 --- a/cpu/o3/commit.hh +++ b/cpu/o3/commit.hh @@ -52,7 +52,6 @@ class SimpleCommit { public: // Typedefs from the Impl. - typedef typename Impl::ISA ISA; typedef typename Impl::FullCPU FullCPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::Params Params; diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh index dc0986772..e289bc0c0 100644 --- a/cpu/o3/commit_impl.hh +++ b/cpu/o3/commit_impl.hh @@ -395,7 +395,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) // Check if the instruction caused a fault. If so, trap. Fault inst_fault = head_inst->getFault(); - if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) { + if (inst_fault != NoFault) { if (!head_inst->isNop()) { #if FULL_SYSTEM cpu->trap(inst_fault); diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 6ea0ed7c7..706657887 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -84,14 +84,14 @@ FullO3CPU<Impl>::FullO3CPU(Params ¶ms) regFile(params.numPhysIntRegs, params.numPhysFloatRegs), - freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs, - Impl::ISA::NumFloatRegs, params.numPhysFloatRegs), + freeList(TheISA::NumIntRegs, params.numPhysIntRegs, + TheISA::NumFloatRegs, params.numPhysFloatRegs), - renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs, - Impl::ISA::NumFloatRegs, params.numPhysFloatRegs, - Impl::ISA::NumMiscRegs, - Impl::ISA::ZeroReg, - Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs), + renameMap(TheISA::NumIntRegs, params.numPhysIntRegs, + TheISA::NumFloatRegs, params.numPhysFloatRegs, + TheISA::NumMiscRegs, + TheISA::ZeroReg, + TheISA::ZeroReg + TheISA::NumIntRegs), rob(params.numROBEntries, params.squashWidth), @@ -253,13 +253,13 @@ FullO3CPU<Impl>::init() ExecContext *src_xc = thread[0]; #endif // First loop through the integer registers. - for (int i = 0; i < Impl::ISA::NumIntRegs; ++i) + for (int i = 0; i < TheISA::NumIntRegs; ++i) { regFile.intRegFile[i] = src_xc->regs.intRegFile[i]; } // Then loop through the floating point registers. - for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i) + for (int i = 0; i < TheISA::NumFloatRegs; ++i) { regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i]; regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i]; diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 75dca5056..321d61dce 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -78,7 +78,6 @@ class FullO3CPU : public BaseFullCPU { public: //Put typedefs from the Impl here. - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPolicy; typedef typename Impl::Params Params; typedef typename Impl::DynInstPtr DynInstPtr; @@ -153,11 +152,11 @@ class FullO3CPU : public BaseFullCPU /** Get instruction asid. */ int getInstAsid() - { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); } + { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); } /** Get data asid. */ int getDataAsid() - { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); } + { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); } #else bool validInstAddr(Addr addr) { return thread[0]->validInstAddr(addr); } diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh index 42313d83a..5b9a0f822 100644 --- a/cpu/o3/decode.hh +++ b/cpu/o3/decode.hh @@ -39,7 +39,6 @@ class SimpleDecode { private: // Typedefs from the Impl. - typedef typename Impl::ISA ISA; typedef typename Impl::FullCPU FullCPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::Params Params; @@ -50,9 +49,6 @@ class SimpleDecode typedef typename CPUPol::DecodeStruct DecodeStruct; typedef typename CPUPol::TimeStruct TimeStruct; - // Typedefs from the ISA. - typedef typename ISA::Addr Addr; - public: // The only time decode will become blocked is if dispatch becomes // blocked, which means IQ or ROB is probably full. diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index 24e445f0b..cc64800d9 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -49,7 +49,6 @@ class SimpleFetch { public: /** Typedefs from Impl. */ - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInst DynInst; typedef typename Impl::DynInstPtr DynInstPtr; @@ -61,7 +60,7 @@ class SimpleFetch typedef typename CPUPol::TimeStruct TimeStruct; /** Typedefs from ISA. */ - typedef typename ISA::MachInst MachInst; + typedef TheISA::MachInst MachInst; public: enum Status { @@ -141,7 +140,7 @@ class SimpleFetch // We fold in the PISA 64- to 32-bit conversion here as well. Addr icacheBlockAlignPC(Addr addr) { - addr = ISA::realPCToFetchPC(addr); + addr = TheISA::realPCToFetchPC(addr); return (addr & ~(cacheBlkMask)); } diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index cd1ed1351..8029fc732 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC) unsigned flags = 0; #endif // FULL_SYSTEM - Fault fault = No_Fault; + Fault fault = NoFault; // Align the fetch PC so it's at the start of a cache block. fetch_PC = icacheBlockAlignPC(fetch_PC); @@ -258,7 +258,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC) // If translation was successful, attempt to read the first // instruction. - if (fault == No_Fault) { + if (fault == NoFault) { DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); fault = cpu->mem->read(memReq, cacheData); // This read may change when the mem interface changes. @@ -268,7 +268,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC) // Now do the timing access to see whether or not the instruction // exists within the cache. - if (icacheInterface && fault == No_Fault) { + if (icacheInterface && fault == NoFault) { DPRINTF(Fetch, "Fetch: Doing timing memory access.\n"); memReq->completionEvent = NULL; @@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch() Addr fetch_PC = cpu->readPC(); // Fault code for memory access. - Fault fault = No_Fault; + Fault fault = NoFault; // If returning from the delay of a cache miss, then update the status // to running, otherwise do the cache access. Possibly move this up @@ -506,7 +506,7 @@ SimpleFetch<Impl>::fetch() unsigned offset = fetch_PC & cacheBlkMask; unsigned fetched; - if (fault == No_Fault) { + if (fault == NoFault) { // If the read of the first instruction was successful, then grab the // instructions from the rest of the cache line and put them into the // queue heading to decode. @@ -582,7 +582,7 @@ SimpleFetch<Impl>::fetch() // Or might want to leave setting the PC to the main CPU, with fetch // only changing the nextPC (will require correct determination of // next PC). - if (fault == No_Fault) { + if (fault == NoFault) { DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC); cpu->setPC(next_PC); cpu->setNextPC(next_PC + instSize); diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh index 733d142fc..0b85dba1e 100644 --- a/cpu/o3/free_list.hh +++ b/cpu/o3/free_list.hh @@ -32,7 +32,7 @@ #include <iostream> #include <queue> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "base/trace.hh" #include "base/traceflags.hh" #include "cpu/o3/comm.hh" diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh index af23c6f45..1e370d4e6 100644 --- a/cpu/o3/iew.hh +++ b/cpu/o3/iew.hh @@ -45,7 +45,6 @@ class SimpleIEW { private: //Typedefs from Impl - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::FullCPU FullCPU; diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh index b8a2b4dc9..85217dd10 100644 --- a/cpu/o3/iew_impl.hh +++ b/cpu/o3/iew_impl.hh @@ -256,7 +256,7 @@ SimpleIEW<Impl>::squashDueToBranch(DynInstPtr &inst) toCommit->branchMispredict = true; // Prediction was incorrect, so send back inverse. toCommit->branchTaken = inst->readNextPC() != - (inst->readPC() + sizeof(MachInst)); + (inst->readPC() + sizeof(TheISA::MachInst)); } template<class Impl> diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh index bbc4162a6..46d98181e 100644 --- a/cpu/o3/ras.hh +++ b/cpu/o3/ras.hh @@ -30,7 +30,7 @@ #define __CPU_O3_CPU_RAS_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" class ReturnAddrStack { diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 4d47b8f9c..ee7b8858e 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -32,6 +32,7 @@ // @todo: Destructor #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" @@ -51,6 +52,10 @@ using namespace EV5; template <class Impl> class PhysRegFile { + protected: + typedef TheISA::IntReg IntReg; + typedef TheISA::FloatReg FloatReg; + typedef TheISA::MiscRegFile MiscRegFile; //Note that most of the definitions of the IntReg, FloatReg, etc. exist //within the Impl/ISA class and not within this PhysRegFile class. @@ -61,7 +66,6 @@ class PhysRegFile //Will make these registers public for now, but they probably should //be private eventually with some accessor functions. public: - typedef typename Impl::ISA ISA; typedef typename Impl::FullCPU FullCPU; PhysRegFile(unsigned _numPhysicalIntRegs, @@ -280,73 +284,73 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault) uint64_t retval = 0; // return value, default 0 switch (idx) { - case ISA::IPR_PALtemp0: - case ISA::IPR_PALtemp1: - case ISA::IPR_PALtemp2: - case ISA::IPR_PALtemp3: - case ISA::IPR_PALtemp4: - case ISA::IPR_PALtemp5: - case ISA::IPR_PALtemp6: - case ISA::IPR_PALtemp7: - case ISA::IPR_PALtemp8: - case ISA::IPR_PALtemp9: - case ISA::IPR_PALtemp10: - case ISA::IPR_PALtemp11: - case ISA::IPR_PALtemp12: - case ISA::IPR_PALtemp13: - case ISA::IPR_PALtemp14: - case ISA::IPR_PALtemp15: - case ISA::IPR_PALtemp16: - case ISA::IPR_PALtemp17: - case ISA::IPR_PALtemp18: - case ISA::IPR_PALtemp19: - case ISA::IPR_PALtemp20: - case ISA::IPR_PALtemp21: - case ISA::IPR_PALtemp22: - case ISA::IPR_PALtemp23: - case ISA::IPR_PAL_BASE: - - case ISA::IPR_IVPTBR: - case ISA::IPR_DC_MODE: - case ISA::IPR_MAF_MODE: - case ISA::IPR_ISR: - case ISA::IPR_EXC_ADDR: - case ISA::IPR_IC_PERR_STAT: - case ISA::IPR_DC_PERR_STAT: - case ISA::IPR_MCSR: - case ISA::IPR_ASTRR: - case ISA::IPR_ASTER: - case ISA::IPR_SIRR: - case ISA::IPR_ICSR: - case ISA::IPR_ICM: - case ISA::IPR_DTB_CM: - case ISA::IPR_IPLR: - case ISA::IPR_INTID: - case ISA::IPR_PMCTR: + case TheISA::IPR_PALtemp0: + case TheISA::IPR_PALtemp1: + case TheISA::IPR_PALtemp2: + case TheISA::IPR_PALtemp3: + case TheISA::IPR_PALtemp4: + case TheISA::IPR_PALtemp5: + case TheISA::IPR_PALtemp6: + case TheISA::IPR_PALtemp7: + case TheISA::IPR_PALtemp8: + case TheISA::IPR_PALtemp9: + case TheISA::IPR_PALtemp10: + case TheISA::IPR_PALtemp11: + case TheISA::IPR_PALtemp12: + case TheISA::IPR_PALtemp13: + case TheISA::IPR_PALtemp14: + case TheISA::IPR_PALtemp15: + case TheISA::IPR_PALtemp16: + case TheISA::IPR_PALtemp17: + case TheISA::IPR_PALtemp18: + case TheISA::IPR_PALtemp19: + case TheISA::IPR_PALtemp20: + case TheISA::IPR_PALtemp21: + case TheISA::IPR_PALtemp22: + case TheISA::IPR_PALtemp23: + case TheISA::IPR_PAL_BASE: + + case TheISA::IPR_IVPTBR: + case TheISA::IPR_DC_MODE: + case TheISA::IPR_MAF_MODE: + case TheISA::IPR_ISR: + case TheISA::IPR_EXC_ADDR: + case TheISA::IPR_IC_PERR_STAT: + case TheISA::IPR_DC_PERR_STAT: + case TheISA::IPR_MCSR: + case TheISA::IPR_ASTRR: + case TheISA::IPR_ASTER: + case TheISA::IPR_SIRR: + case TheISA::IPR_ICSR: + case TheISA::IPR_ICM: + case TheISA::IPR_DTB_CM: + case TheISA::IPR_IPLR: + case TheISA::IPR_INTID: + case TheISA::IPR_PMCTR: // no side-effect retval = ipr[idx]; break; - case ISA::IPR_CC: + case TheISA::IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); retval |= curTick & ULL(0x00000000ffffffff); break; - case ISA::IPR_VA: + case TheISA::IPR_VA: retval = ipr[idx]; break; - case ISA::IPR_VA_FORM: - case ISA::IPR_MM_STAT: - case ISA::IPR_IFAULT_VA_FORM: - case ISA::IPR_EXC_MASK: - case ISA::IPR_EXC_SUM: + case TheISA::IPR_VA_FORM: + case TheISA::IPR_MM_STAT: + case TheISA::IPR_IFAULT_VA_FORM: + case TheISA::IPR_EXC_MASK: + case TheISA::IPR_EXC_SUM: retval = ipr[idx]; break; - case ISA::IPR_DTB_PTE: + case TheISA::IPR_DTB_PTE: { - typename ISA::PTE &pte = cpu->dtb->index(1); + TheISA::PTE &pte = cpu->dtb->index(1); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; @@ -359,21 +363,21 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault) break; // write only registers - case ISA::IPR_HWINT_CLR: - case ISA::IPR_SL_XMIT: - case ISA::IPR_DC_FLUSH: - case ISA::IPR_IC_FLUSH: - case ISA::IPR_ALT_MODE: - case ISA::IPR_DTB_IA: - case ISA::IPR_DTB_IAP: - case ISA::IPR_ITB_IA: - case ISA::IPR_ITB_IAP: - fault = Unimplemented_Opcode_Fault; + case TheISA::IPR_HWINT_CLR: + case TheISA::IPR_SL_XMIT: + case TheISA::IPR_DC_FLUSH: + case TheISA::IPR_IC_FLUSH: + case TheISA::IPR_ALT_MODE: + case TheISA::IPR_DTB_IA: + case TheISA::IPR_DTB_IAP: + case TheISA::IPR_ITB_IA: + case TheISA::IPR_ITB_IAP: + fault = UnimplementedOpcodeFault; break; default: // invalid IPR - fault = Unimplemented_Opcode_Fault; + fault = UnimplementedOpcodeFault; break; } @@ -389,195 +393,195 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) uint64_t old; switch (idx) { - case ISA::IPR_PALtemp0: - case ISA::IPR_PALtemp1: - case ISA::IPR_PALtemp2: - case ISA::IPR_PALtemp3: - case ISA::IPR_PALtemp4: - case ISA::IPR_PALtemp5: - case ISA::IPR_PALtemp6: - case ISA::IPR_PALtemp7: - case ISA::IPR_PALtemp8: - case ISA::IPR_PALtemp9: - case ISA::IPR_PALtemp10: - case ISA::IPR_PALtemp11: - case ISA::IPR_PALtemp12: - case ISA::IPR_PALtemp13: - case ISA::IPR_PALtemp14: - case ISA::IPR_PALtemp15: - case ISA::IPR_PALtemp16: - case ISA::IPR_PALtemp17: - case ISA::IPR_PALtemp18: - case ISA::IPR_PALtemp19: - case ISA::IPR_PALtemp20: - case ISA::IPR_PALtemp21: - case ISA::IPR_PALtemp22: - case ISA::IPR_PAL_BASE: - case ISA::IPR_IC_PERR_STAT: - case ISA::IPR_DC_PERR_STAT: - case ISA::IPR_PMCTR: + case TheISA::IPR_PALtemp0: + case TheISA::IPR_PALtemp1: + case TheISA::IPR_PALtemp2: + case TheISA::IPR_PALtemp3: + case TheISA::IPR_PALtemp4: + case TheISA::IPR_PALtemp5: + case TheISA::IPR_PALtemp6: + case TheISA::IPR_PALtemp7: + case TheISA::IPR_PALtemp8: + case TheISA::IPR_PALtemp9: + case TheISA::IPR_PALtemp10: + case TheISA::IPR_PALtemp11: + case TheISA::IPR_PALtemp12: + case TheISA::IPR_PALtemp13: + case TheISA::IPR_PALtemp14: + case TheISA::IPR_PALtemp15: + case TheISA::IPR_PALtemp16: + case TheISA::IPR_PALtemp17: + case TheISA::IPR_PALtemp18: + case TheISA::IPR_PALtemp19: + case TheISA::IPR_PALtemp20: + case TheISA::IPR_PALtemp21: + case TheISA::IPR_PALtemp22: + case TheISA::IPR_PAL_BASE: + case TheISA::IPR_IC_PERR_STAT: + case TheISA::IPR_DC_PERR_STAT: + case TheISA::IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; - case ISA::IPR_CC_CTL: + case TheISA::IPR_CC_CTL: // This IPR resets the cycle counter. We assume this only // happens once... let's verify that. assert(ipr[idx] == 0); ipr[idx] = 1; break; - case ISA::IPR_CC: + case TheISA::IPR_CC: // This IPR only writes the upper 64 bits. It's ok to write // all 64 here since we mask out the lower 32 in rpcc (see // isa_desc). ipr[idx] = val; break; - case ISA::IPR_PALtemp23: + case TheISA::IPR_PALtemp23: // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; break; - case ISA::IPR_DTB_PTE: + case TheISA::IPR_DTB_PTE: // write entire quad w/ no side-effect, tag is forthcoming ipr[idx] = val; break; - case ISA::IPR_EXC_ADDR: + case TheISA::IPR_EXC_ADDR: // second least significant bit in PC is always zero ipr[idx] = val & ~2; break; - case ISA::IPR_ASTRR: - case ISA::IPR_ASTER: + case TheISA::IPR_ASTRR: + case TheISA::IPR_ASTER: // only write least significant four bits - privilege mask ipr[idx] = val & 0xf; break; - case ISA::IPR_IPLR: + case TheISA::IPR_IPLR: // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; break; - case ISA::IPR_DTB_CM: + case TheISA::IPR_DTB_CM: - case ISA::IPR_ICM: + case TheISA::IPR_ICM: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case ISA::IPR_ALT_MODE: + case TheISA::IPR_ALT_MODE: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case ISA::IPR_MCSR: + case TheISA::IPR_MCSR: // more here after optimization... ipr[idx] = val; break; - case ISA::IPR_SIRR: + case TheISA::IPR_SIRR: // only write software interrupt mask ipr[idx] = val & 0x7fff0; break; - case ISA::IPR_ICSR: + case TheISA::IPR_ICSR: ipr[idx] = val & ULL(0xffffff0300); break; - case ISA::IPR_IVPTBR: - case ISA::IPR_MVPTBR: + case TheISA::IPR_IVPTBR: + case TheISA::IPR_MVPTBR: ipr[idx] = val & ULL(0xffffffffc0000000); break; - case ISA::IPR_DC_TEST_CTL: + case TheISA::IPR_DC_TEST_CTL: ipr[idx] = val & 0x1ffb; break; - case ISA::IPR_DC_MODE: - case ISA::IPR_MAF_MODE: + case TheISA::IPR_DC_MODE: + case TheISA::IPR_MAF_MODE: ipr[idx] = val & 0x3f; break; - case ISA::IPR_ITB_ASN: + case TheISA::IPR_ITB_ASN: ipr[idx] = val & 0x7f0; break; - case ISA::IPR_DTB_ASN: + case TheISA::IPR_DTB_ASN: ipr[idx] = val & ULL(0xfe00000000000000); break; - case ISA::IPR_EXC_SUM: - case ISA::IPR_EXC_MASK: + case TheISA::IPR_EXC_SUM: + case TheISA::IPR_EXC_MASK: // any write to this register clears it ipr[idx] = 0; break; - case ISA::IPR_INTID: - case ISA::IPR_SL_RCV: - case ISA::IPR_MM_STAT: - case ISA::IPR_ITB_PTE_TEMP: - case ISA::IPR_DTB_PTE_TEMP: + case TheISA::IPR_INTID: + case TheISA::IPR_SL_RCV: + case TheISA::IPR_MM_STAT: + case TheISA::IPR_ITB_PTE_TEMP: + case TheISA::IPR_DTB_PTE_TEMP: // read-only registers - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; - case ISA::IPR_HWINT_CLR: - case ISA::IPR_SL_XMIT: - case ISA::IPR_DC_FLUSH: - case ISA::IPR_IC_FLUSH: + case TheISA::IPR_HWINT_CLR: + case TheISA::IPR_SL_XMIT: + case TheISA::IPR_DC_FLUSH: + case TheISA::IPR_IC_FLUSH: // the following are write only ipr[idx] = val; break; - case ISA::IPR_DTB_IA: + case TheISA::IPR_DTB_IA: // really a control write ipr[idx] = 0; cpu->dtb->flushAll(); break; - case ISA::IPR_DTB_IAP: + case TheISA::IPR_DTB_IAP: // really a control write ipr[idx] = 0; cpu->dtb->flushProcesses(); break; - case ISA::IPR_DTB_IS: + case TheISA::IPR_DTB_IS: // really a control write ipr[idx] = val; - cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN])); + cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN])); break; - case ISA::IPR_DTB_TAG: { - struct ISA::PTE pte; + case TheISA::IPR_DTB_TAG: { + struct TheISA::PTE pte; // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0) + if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0) panic("PTE GH field != 0"); // write entire quad ipr[idx] = val; // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]); + pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]); + pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]); + pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]); + pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]); + pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]); + pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]); + pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB cpu->dtb->insert(val, pte); } break; - case ISA::IPR_ITB_PTE: { - struct ISA::PTE pte; + case TheISA::IPR_ITB_PTE: { + struct TheISA::PTE pte; // FIXME: granularity hints NYI... if (ITB_PTE_GH(val) != 0) @@ -593,41 +597,41 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) pte.fonr = ITB_PTE_FONR(val); pte.fonw = ITB_PTE_FONW(val); pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]); + pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte); + cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte); } break; - case ISA::IPR_ITB_IA: + case TheISA::IPR_ITB_IA: // really a control write ipr[idx] = 0; cpu->itb->flushAll(); break; - case ISA::IPR_ITB_IAP: + case TheISA::IPR_ITB_IAP: // really a control write ipr[idx] = 0; cpu->itb->flushProcesses(); break; - case ISA::IPR_ITB_IS: + case TheISA::IPR_ITB_IS: // really a control write ipr[idx] = val; - cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN])); + cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN])); break; default: // invalid IPR - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; } // no error... - return No_Fault; + return NoFault; } #endif // #if FULL_SYSTEM diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh index a17ec7311..07b442964 100644 --- a/cpu/o3/rename.hh +++ b/cpu/o3/rename.hh @@ -46,7 +46,6 @@ class SimpleRename { public: // Typedefs from the Impl. - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::FullCPU FullCPU; @@ -62,7 +61,7 @@ class SimpleRename typedef typename CPUPol::RenameMap RenameMap; // Typedefs from the ISA. - typedef typename ISA::Addr Addr; + typedef TheISA::RegIndex RegIndex; public: // Rename will block if ROB becomes full or issue queue becomes full, diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh index c44c7a1ea..57be4a64a 100644 --- a/cpu/o3/rename_map.hh +++ b/cpu/o3/rename_map.hh @@ -38,9 +38,13 @@ #include <vector> #include "cpu/o3/free_list.hh" +//For RegIndex +#include "arch/isa_traits.hh" class SimpleRenameMap { + protected: + typedef TheISA::RegIndex RegIndex; public: /** * Pair of a logical register and a physical register. Tells the diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh index 29ec48007..1185564ad 100644 --- a/cpu/o3/rob.hh +++ b/cpu/o3/rob.hh @@ -47,6 +47,8 @@ template <class Impl> class ROB { + protected: + typedef TheISA::RegIndex RegIndex; public: //Typedefs from the Impl. typedef typename Impl::FullCPU FullCPU; diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh index bcd590384..5a885d838 100644 --- a/cpu/o3/store_set.hh +++ b/cpu/o3/store_set.hh @@ -31,7 +31,7 @@ #include <vector> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" class StoreSet diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh index 58ea1a7d9..cb93c2f67 100644 --- a/cpu/o3/tournament_pred.hh +++ b/cpu/o3/tournament_pred.hh @@ -30,7 +30,7 @@ #define __CPU_O3_CPU_TOURNAMENT_PRED_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/o3/sat_counter.hh" class TournamentBP diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh index 5af77862a..667e2b3f8 100644 --- a/cpu/ozone/cpu.hh +++ b/cpu/ozone/cpu.hh @@ -77,7 +77,6 @@ class OoOCPU : public BaseCPU private: typedef typename Impl::DynInst DynInst; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::ISA ISA; public: // main simulation loop (one cycle) @@ -320,7 +319,7 @@ class OoOCPU : public BaseCPU // put the asid in the upper 16 bits of the paddr req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; - return No_Fault; + return NoFault; } Fault translateInstReq(MemReqPtr &req) { @@ -378,12 +377,12 @@ class OoOCPU : public BaseCPU private: InstSeqNum globalSeqNum; - DynInstPtr renameTable[ISA::TotalNumRegs]; - DynInstPtr commitTable[ISA::TotalNumRegs]; + DynInstPtr renameTable[TheISA::TotalNumRegs]; + DynInstPtr commitTable[TheISA::TotalNumRegs]; // Might need a table of the shadow registers as well. #if FULL_SYSTEM - DynInstPtr palShadowTable[ISA::NumIntRegs]; + DynInstPtr palShadowTable[TheISA::NumIntRegs]; #endif public: @@ -402,47 +401,47 @@ class OoOCPU : public BaseCPU // rename table of DynInsts. Also these likely shouldn't be called very // often, other than when adding things into the xc during say a syscall. - uint64_t readIntReg(StaticInst<TheISA> *si, int idx) + uint64_t readIntReg(StaticInst *si, int idx) { return xc->readIntReg(si->srcRegIdx(idx)); } - float readFloatRegSingle(StaticInst<TheISA> *si, int idx) + float readFloatRegSingle(StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegSingle(reg_idx); } - double readFloatRegDouble(StaticInst<TheISA> *si, int idx) + double readFloatRegDouble(StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegDouble(reg_idx); } - uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx) + uint64_t readFloatRegInt(StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegInt(reg_idx); } - void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val) + void setIntReg(StaticInst *si, int idx, uint64_t val) { xc->setIntReg(si->destRegIdx(idx), val); } - void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val) + void setFloatRegSingle(StaticInst *si, int idx, float val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegSingle(reg_idx, val); } - void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val) + void setFloatRegDouble(StaticInst *si, int idx, double val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegDouble(reg_idx, val); } - void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val) + void setFloatRegInt(StaticInst *si, int idx, uint64_t val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegInt(reg_idx, val); @@ -479,7 +478,7 @@ class OoOCPU : public BaseCPU // We fold in the PISA 64- to 32-bit conversion here as well. Addr icacheBlockAlignPC(Addr addr) { - addr = ISA::realPCToFetchPC(addr); + addr = TheISA::realPCToFetchPC(addr); return (addr & ~(cacheBlkMask)); } @@ -545,18 +544,18 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst) Fault fault = translateDataReadReq(readReq); // do functional access - if (fault == No_Fault) + if (fault == NoFault) fault = xc->mem->read(readReq, data); #if 0 if (traceData) { traceData->setAddr(addr); - if (fault == No_Fault) + if (fault == NoFault) traceData->setData(data); } #endif // if we have a cache, do cache access too - if (fault == No_Fault && dcacheInterface) { + if (fault == NoFault && dcacheInterface) { readReq->cmd = Read; readReq->completionEvent = NULL; readReq->time = curTick; @@ -598,10 +597,10 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags, Fault fault = translateDataWriteReq(writeReq); // do functional access - if (fault == No_Fault) + if (fault == NoFault) fault = xc->write(writeReq, data); - if (fault == No_Fault && dcacheInterface) { + if (fault == NoFault && dcacheInterface) { writeReq->cmd = Write; memcpy(writeReq->data,(uint8_t *)&data,writeReq->size); writeReq->completionEvent = NULL; @@ -614,7 +613,7 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags, } } - if (res && (fault == No_Fault)) + if (res && (fault == NoFault)) *res = writeReq->result; if (!dcacheInterface && (writeReq->flags & UNCACHEABLE)) diff --git a/cpu/profile.hh b/cpu/profile.hh index 58cd7e79f..18061f9bf 100644 --- a/cpu/profile.hh +++ b/cpu/profile.hh @@ -68,7 +68,7 @@ class FunctionProfile FunctionProfile(const SymbolTable *symtab); ~FunctionProfile(); - ProfileNode *consume(ExecContext *xc, StaticInstPtr<TheISA> inst); + ProfileNode *consume(ExecContext *xc, StaticInstPtr inst); ProfileNode *consume(const std::vector<Addr> &stack); void clear(); void dump(ExecContext *xc, std::ostream &out) const; @@ -76,7 +76,7 @@ class FunctionProfile }; inline ProfileNode * -FunctionProfile::consume(ExecContext *xc, StaticInstPtr<TheISA> inst) +FunctionProfile::consume(ExecContext *xc, StaticInstPtr inst) { if (!trace.trace(xc, inst)) return NULL; diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 2438e49f6..944bdbb0a 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -76,7 +76,7 @@ using namespace std; //The SimpleCPU does alpha only -using namespace LittleEndianGuest; +using namespace AlphaISA; SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) @@ -336,7 +336,7 @@ SimpleCPU::copySrcTranslate(Addr src) // Make sure block doesn't span page if (no_warn && - (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) && + (src & PageMask) != ((src + blk_size) & PageMask) && (src >> 40) != 0xfffffc) { warn("Copied block source spans pages %x.", src); no_warn = false; @@ -347,9 +347,9 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(memReq); - assert(fault != Alignment_Fault); + assert(fault != AlignmentFault); - if (fault == No_Fault) { + if (fault == NoFault) { xc->copySrcAddr = src; xc->copySrcPhysAddr = memReq->paddr + offset; } else { @@ -372,7 +372,7 @@ SimpleCPU::copy(Addr dest) // Make sure block doesn't span page if (no_warn && - (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) && + (dest & PageMask) != ((dest + blk_size) & PageMask) && (dest >> 40) != 0xfffffc) { no_warn = false; warn("Copied block destination spans pages %x. ", dest); @@ -382,9 +382,9 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(memReq); - assert(fault != Alignment_Fault); + assert(fault != AlignmentFault); - if (fault == No_Fault) { + if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. memReq->paddr = xc->copySrcPhysAddr; @@ -425,7 +425,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) Fault fault = xc->translateDataReadReq(memReq); // if we have a cache, do cache access too - if (fault == No_Fault && dcacheInterface) { + if (fault == NoFault && dcacheInterface) { memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; @@ -445,7 +445,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) fault = xc->read(memReq, data); } - } else if(fault == No_Fault) { + } else if(fault == NoFault) { // do functional access fault = xc->read(memReq, data); @@ -510,10 +510,10 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) Fault fault = xc->translateDataWriteReq(memReq); // do functional access - if (fault == No_Fault) + if (fault == NoFault) fault = xc->write(memReq, data); - if (fault == No_Fault && dcacheInterface) { + if (fault == NoFault && dcacheInterface) { memReq->cmd = Write; memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; @@ -532,7 +532,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } } - if (res && (fault == No_Fault)) + if (res && (fault == NoFault)) *res = memReq->result; if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) @@ -651,7 +651,7 @@ SimpleCPU::tick() traceData = NULL; - Fault fault = No_Fault; + Fault fault = NoFault; #if FULL_SYSTEM if (checkInterrupts && check_interrupts() && !xc->inPalMode() && @@ -661,20 +661,20 @@ SimpleCPU::tick() checkInterrupts = false; IntReg *ipr = xc->regs.ipr; - if (xc->regs.ipr[TheISA::IPR_SIRR]) { - for (int i = TheISA::INTLEVEL_SOFTWARE_MIN; - i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) { - if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) { + if (xc->regs.ipr[IPR_SIRR]) { + for (int i = INTLEVEL_SOFTWARE_MIN; + i < INTLEVEL_SOFTWARE_MAX; i++) { + if (ipr[IPR_SIRR] & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference - ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1; + ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); } } } uint64_t interrupts = xc->cpu->intr_status(); - for (int i = TheISA::INTLEVEL_EXTERNAL_MIN; - i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) { + for (int i = INTLEVEL_EXTERNAL_MIN; + i < INTLEVEL_EXTERNAL_MAX; i++) { if (interrupts & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference ipl = i; @@ -682,16 +682,16 @@ SimpleCPU::tick() } } - if (ipr[TheISA::IPR_ASTRR]) + if (ipr[IPR_ASTRR]) panic("asynchronous traps not implemented\n"); - if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) { - ipr[TheISA::IPR_ISR] = summary; - ipr[TheISA::IPR_INTID] = ipl; - xc->ev5_trap(Interrupt_Fault); + if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { + ipr[IPR_ISR] = summary; + ipr[IPR_INTID] = ipl; + xc->ev5_trap(InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - ipr[TheISA::IPR_IPLR], ipl, summary); + ipr[IPR_IPLR], ipl, summary); } } #endif @@ -726,10 +726,10 @@ SimpleCPU::tick() fault = xc->translateInstReq(memReq); - if (fault == No_Fault) + if (fault == NoFault) fault = xc->mem->read(memReq, inst); - if (icacheInterface && fault == No_Fault) { + if (icacheInterface && fault == NoFault) { memReq->completionEvent = NULL; memReq->time = curTick; @@ -751,7 +751,7 @@ SimpleCPU::tick() // If we've got a valid instruction (i.e., no fault on instruction // fetch), then execute it. - if (fault == No_Fault) { + if (fault == NoFault) { // keep an instruction count numInst++; @@ -762,7 +762,7 @@ SimpleCPU::tick() // decode the instruction inst = gtoh(inst); - curStaticInst = StaticInst<TheISA>::decode(inst); + curStaticInst = StaticInst::decode(inst); traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst, xc->regs.pc); @@ -808,9 +808,9 @@ SimpleCPU::tick() traceFunctions(xc->regs.pc); - } // if (fault == No_Fault) + } // if (fault == NoFault) - if (fault != No_Fault) { + if (fault != NoFault) { #if FULL_SYSTEM xc->ev5_trap(fault); #else // !FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 564749592..ed7b1e29b 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -63,6 +63,8 @@ namespace Trace { class SimpleCPU : public BaseCPU { + protected: + typedef TheISA::MachInst MachInst; public: // main simulation loop (one cycle) void tick(); @@ -173,7 +175,7 @@ class SimpleCPU : public BaseCPU // the next switchover Sampler *sampler; - StaticInstPtr<TheISA> curStaticInst; + StaticInstPtr curStaticInst; class CacheCompletionEvent : public Event { @@ -270,47 +272,47 @@ class SimpleCPU : public BaseCPU // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst<TheISA> *si, int idx) + uint64_t readIntReg(const StaticInst *si, int idx) { return xc->readIntReg(si->srcRegIdx(idx)); } - float readFloatRegSingle(const StaticInst<TheISA> *si, int idx) + float readFloatRegSingle(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegSingle(reg_idx); } - double readFloatRegDouble(const StaticInst<TheISA> *si, int idx) + double readFloatRegDouble(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegDouble(reg_idx); } - uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx) + uint64_t readFloatRegInt(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegInt(reg_idx); } - void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val) + void setIntReg(const StaticInst *si, int idx, uint64_t val) { xc->setIntReg(si->destRegIdx(idx), val); } - void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val) + void setFloatRegSingle(const StaticInst *si, int idx, float val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegSingle(reg_idx, val); } - void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val) + void setFloatRegDouble(const StaticInst *si, int idx, double val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegDouble(reg_idx, val); } - void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val) + void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegInt(reg_idx, val); diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc index 54bd9914e..c307dc6fc 100644 --- a/cpu/static_inst.cc +++ b/cpu/static_inst.cc @@ -30,19 +30,13 @@ #include "cpu/static_inst.hh" #include "sim/root.hh" -template <class ISA> -StaticInstPtr<ISA> StaticInst<ISA>::nullStaticInstPtr; - -template <class ISA> -typename StaticInst<ISA>::DecodeCache StaticInst<ISA>::decodeCache; +StaticInstPtr StaticInst::nullStaticInstPtr; // Define the decode cache hash map. -template StaticInst<AlphaISA>::DecodeCache -StaticInst<AlphaISA>::decodeCache; +StaticInst::DecodeCache StaticInst::decodeCache; -template <class ISA> void -StaticInst<ISA>::dumpDecodeCacheStats() +StaticInst::dumpDecodeCacheStats() { using namespace std; @@ -62,13 +56,8 @@ StaticInst<ISA>::dumpDecodeCacheStats() } } - -template StaticInstPtr<AlphaISA> -StaticInst<AlphaISA>::nullStaticInstPtr; - -template <class ISA> bool -StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const +StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const { if (isDirectCtrl()) { tgt = branchTarget(pc); @@ -83,6 +72,3 @@ StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const return false; } - -// force instantiation of template function(s) above -template class StaticInst<AlphaISA>; diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 24997eadc..5106dcf06 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -113,6 +113,8 @@ class StaticInstBase : public RefCounted IsSerializing, ///< Serializes pipeline: won't execute until all /// older instructions have committed. + IsSerializeBefore, + IsSerializeAfter, IsMemBarrier, ///< Is a memory barrier IsWriteBarrier, ///< Is a write barrier @@ -196,7 +198,11 @@ class StaticInstBase : public RefCounted bool isUncondCtrl() const { return flags[IsUncondControl]; } bool isThreadSync() const { return flags[IsThreadSync]; } - bool isSerializing() const { return flags[IsSerializing]; } + bool isSerializing() const { return flags[IsSerializing] || + flags[IsSerializeBefore] || + flags[IsSerializeAfter]; } + bool isSerializeBefore() const { return flags[IsSerializeBefore]; } + bool isSerializeAfter() const { return flags[IsSerializeAfter]; } bool isMemBarrier() const { return flags[IsMemBarrier]; } bool isWriteBarrier() const { return flags[IsWriteBarrier]; } bool isNonSpeculative() const { return flags[IsNonSpeculative]; } @@ -208,7 +214,6 @@ class StaticInstBase : public RefCounted // forward declaration -template <class ISA> class StaticInstPtr; /** @@ -218,21 +223,18 @@ class StaticInstPtr; * that are generic across all ISAs but that differ in details * according to the specific ISA being used. */ -template <class ISA> class StaticInst : public StaticInstBase { public: /// Binary machine instruction type. - typedef typename ISA::MachInst MachInst; - /// Memory address type. - typedef typename ISA::Addr Addr; + typedef TheISA::MachInst MachInst; /// Logical register index type. - typedef typename ISA::RegIndex RegIndex; + typedef TheISA::RegIndex RegIndex; enum { - MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs - MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs + MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs + MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs }; @@ -247,7 +249,7 @@ class StaticInst : public StaticInstBase /// Pointer to a statically allocated "null" instruction object. /// Used to give eaCompInst() and memAccInst() something to return /// when called on non-memory instructions. - static StaticInstPtr<ISA> nullStaticInstPtr; + static StaticInstPtr nullStaticInstPtr; /** * Memory references only: returns "fake" instruction representing @@ -256,7 +258,7 @@ class StaticInst : public StaticInstBase * just the EA computation. */ virtual const - StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; } + StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } /** * Memory references only: returns "fake" instruction representing @@ -265,7 +267,7 @@ class StaticInst : public StaticInstBase * just the memory access (not the EA computation). */ virtual const - StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; } + StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } /// The binary machine instruction. const MachInst machInst; @@ -364,7 +366,7 @@ class StaticInst : public StaticInstBase /// Decoded instruction cache type. /// For now we're using a generic hash_map; this seems to work /// pretty well. - typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache; + typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache; /// A cache of decoded instruction objects. static DecodeCache decodeCache; @@ -378,63 +380,40 @@ class StaticInst : public StaticInstBase /// Decode a machine instruction. /// @param mach_inst The binary instruction to decode. /// @retval A pointer to the corresponding StaticInst object. - static - StaticInstPtr<ISA> decode(MachInst mach_inst) - { -#ifdef DECODE_CACHE_HASH_STATS - // Simple stats on decode hash_map. Turns out the default - // hash function is as good as anything I could come up with. - const int dump_every_n = 10000000; - static int decodes_til_dump = dump_every_n; - - if (--decodes_til_dump == 0) { - dumpDecodeCacheStats(); - decodes_til_dump = dump_every_n; - } -#endif - - typename DecodeCache::iterator iter = decodeCache.find(mach_inst); - if (iter != decodeCache.end()) { - return iter->second; - } - - StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst); - decodeCache[mach_inst] = si; - return si; - } + //This is defined as inline below. + static StaticInstPtr decode(MachInst mach_inst); }; typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; /// Reference-counted pointer to a StaticInst object. -/// This type should be used instead of "StaticInst<ISA> *" so that +/// This type should be used instead of "StaticInst *" so that /// StaticInst objects can be properly reference-counted. -template <class ISA> -class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> > +class StaticInstPtr : public RefCountingPtr<StaticInst> { public: /// Constructor. StaticInstPtr() - : RefCountingPtr<StaticInst<ISA> >() + : RefCountingPtr<StaticInst>() { } - /// Conversion from "StaticInst<ISA> *". - StaticInstPtr(StaticInst<ISA> *p) - : RefCountingPtr<StaticInst<ISA> >(p) + /// Conversion from "StaticInst *". + StaticInstPtr(StaticInst *p) + : RefCountingPtr<StaticInst>(p) { } /// Copy constructor. StaticInstPtr(const StaticInstPtr &r) - : RefCountingPtr<StaticInst<ISA> >(r) + : RefCountingPtr<StaticInst>(r) { } /// Construct directly from machine instruction. - /// Calls StaticInst<ISA>::decode(). - StaticInstPtr(typename ISA::MachInst mach_inst) - : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst)) + /// Calls StaticInst::decode(). + StaticInstPtr(TheISA::MachInst mach_inst) + : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst)) { } @@ -445,4 +424,29 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> > } }; +inline StaticInstPtr +StaticInst::decode(StaticInst::MachInst mach_inst) +{ +#ifdef DECODE_CACHE_HASH_STATS + // Simple stats on decode hash_map. Turns out the default + // hash function is as good as anything I could come up with. + const int dump_every_n = 10000000; + static int decodes_til_dump = dump_every_n; + + if (--decodes_til_dump == 0) { + dumpDecodeCacheStats(); + decodes_til_dump = dump_every_n; + } +#endif + + DecodeCache::iterator iter = decodeCache.find(mach_inst); + if (iter != decodeCache.end()) { + return iter->second; + } + + StaticInstPtr si = TheISA::decodeInst(mach_inst); + decodeCache[mach_inst] = si; + return si; +} + #endif // __CPU_STATIC_INST_HH__ diff --git a/cpu/trace/reader/itx_reader.hh b/cpu/trace/reader/itx_reader.hh index faec73138..a16a08085 100644 --- a/cpu/trace/reader/itx_reader.hh +++ b/cpu/trace/reader/itx_reader.hh @@ -46,6 +46,7 @@ */ class ITXReader : public MemTraceReader { + private: /** Trace file. */ FILE *trace; |