diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/cpu_exec_context.cc | 65 | ||||
| -rw-r--r-- | cpu/cpu_exec_context.hh | 121 | ||||
| -rw-r--r-- | cpu/exec_context.hh | 49 | ||||
| -rw-r--r-- | cpu/exetrace.cc | 12 | ||||
| -rw-r--r-- | cpu/exetrace.hh | 2 | ||||
| -rw-r--r-- | cpu/simple/cpu.cc | 87 | ||||
| -rw-r--r-- | cpu/simple/cpu.hh | 13 |
7 files changed, 219 insertions, 130 deletions
diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index 0a3dc5675..62419adcf 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -42,10 +42,10 @@ #include "kern/kernel_stats.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" -#include "sim/system.hh" #include "arch/stacktrace.hh" #else #include "sim/process.hh" +#include "sim/system.hh" #include "mem/translating_port.hh" #endif @@ -54,16 +54,16 @@ using namespace std; // constructor #if FULL_SYSTEM CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, - AlphaITB *_itb, AlphaDTB *_dtb, - Memory *_mem) + AlphaITB *_itb, AlphaDTB *_dtb) : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num), - cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb), - dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem), - profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0) + cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb), + dtb(_dtb), profile(NULL), quiesceEvent(this), func_exe_inst(0), + storeCondFailures(0) + { proxy = new ProxyExecContext<CPUExecContext>(this); - memset(®s, 0, sizeof(RegFile)); + regs.clear(); if (cpu->params->profile) { profile = new FunctionProfile(system->kernelSymtab); @@ -78,17 +78,34 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, static ProfileNode dummyNode; profileNode = &dummyNode; profilePC = 3; + + Port *mem_port; + physPort = new FunctionalPort(); + mem_port = system->physmem->getPort("functional"); + mem_port->setPeer(physPort); + physPort->setPeer(mem_port); + + virtPort = new VirtualPort(); + mem_port = system->physmem->getPort("functional"); + mem_port->setPeer(virtPort); + virtPort->setPeer(mem_port); } #else CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, - Process *_process, int _asid, Port *mem_port) + Process *_process, int _asid, MemObject* memobj) : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0), lastSuspend(0), process(_process), asid(_asid), func_exe_inst(0), storeCondFailures(0) { - port = new TranslatingPort(mem_port, process->pTable); - memset(®s, 0, sizeof(RegFile)); + /* Use this port to for syscall emulation writes to memory. */ + Port *mem_port; + port = new TranslatingPort(process->pTable, false); + mem_port = memobj->getPort("functional"); + mem_port->setPeer(port); + port->setPeer(mem_port); + + regs.clear(); proxy = new ProxyExecContext<CPUExecContext>(this); } @@ -273,3 +290,31 @@ CPUExecContext::copyArchRegs(ExecContext *xc) TheISA::copyRegs(xc, proxy); } +#if FULL_SYSTEM +VirtualPort* +CPUExecContext::getVirtPort(ExecContext *xc) +{ + if (!xc) + return virtPort; + + VirtualPort *vp; + Port *mem_port; + + vp = new VirtualPort(xc); + mem_port = system->physmem->getPort("functional"); + mem_port->setPeer(vp); + vp->setPeer(mem_port); + return vp; +} + +void +CPUExecContext::delVirtPort(VirtualPort *vp) +{ + assert(!vp->nullExecContext()); + delete vp->getPeer(); + delete vp; +} + + +#endif + diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 236619752..eb5d712b9 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -48,7 +48,9 @@ class BaseCPU; class FunctionProfile; class ProfileNode; -class MemoryController; +class FunctionalPort; +class PhysicalPort; + #else // !FULL_SYSTEM @@ -56,6 +58,7 @@ class MemoryController; #include "mem/page_table.hh" class TranslatingPort; + #endif // FULL_SYSTEM // @@ -121,19 +124,18 @@ class CPUExecContext System *system; - /// Port that syscalls can use to access memory (provides translation step). - TranslatingPort *port; -// Memory *mem; #if FULL_SYSTEM AlphaITB *itb; AlphaDTB *dtb; - // the following two fields are redundant, since we can always - // look them up through the system pointer, but we'll leave them - // here for now for convenience - MemoryController *memctrl; -// PhysicalMemory *physmem; + /** A functional port outgoing only for functional accesses to physical + * addresses.*/ + FunctionalPort *physPort; + + /** A functional port, outgoing only, for functional accesse to virtual + * addresses. That doen't require execution context information */ + VirtualPort *virtPort; FunctionProfile *profile; ProfileNode *profileNode; @@ -167,6 +169,9 @@ class CPUExecContext void profileSample(); #else + /// Port that syscalls can use to access memory (provides translation step). + TranslatingPort *port; + Process *process; // Address space ID. Note that this is used for TIMING cache @@ -203,9 +208,10 @@ class CPUExecContext // constructor: initialize context from given process structure #if FULL_SYSTEM CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system, - AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); + AlphaITB *_itb, AlphaDTB *_dtb); #else - CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, Port *mem_port); + CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, + MemObject *memobj); // Constructor to use XC to pass reg file around. Not used for anything // else. CPUExecContext(RegFile *regFile); @@ -219,8 +225,6 @@ class CPUExecContext void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); - TranslatingPort *getMemPort() { return port; } - BaseCPU *getCpuPtr() { return cpu; } ExecContext *getProxy() { return proxy; } @@ -230,8 +234,6 @@ class CPUExecContext #if FULL_SYSTEM System *getSystemPtr() { return system; } - PhysicalMemory *getPhysMemPtr() { return physmem; } - AlphaITB *getITBPtr() { return itb; } AlphaDTB *getDTBPtr() { return dtb; } @@ -239,38 +241,49 @@ class CPUExecContext int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } - Fault translateInstReq(CpuRequestPtr &req) + Fault translateInstReq(RequestPtr &req) { - return itb->translate(req); + return itb->translate(req, proxy); } - Fault translateDataReadReq(CpuRequestPtr &req) + Fault translateDataReadReq(RequestPtr &req) { - return dtb->translate(req, false); + return dtb->translate(req, proxy, false); } - Fault translateDataWriteReq(CpuRequestPtr &req) + Fault translateDataWriteReq(RequestPtr &req) { - return dtb->translate(req, true); + return dtb->translate(req, proxy, true); } + FunctionalPort *getPhysPort() { return physPort; } + + /** Return a virtual port. If no exec context is specified then a static + * port is returned. Otherwise a port is created and returned. It must be + * deleted by deleteVirtPort(). */ + VirtualPort *getVirtPort(ExecContext *xc); + + void delVirtPort(VirtualPort *vp); + #else + TranslatingPort *getMemPort() { return port; } + Process *getProcessPtr() { return process; } int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault translateInstReq(CpuRequestPtr &req) + Fault translateInstReq(RequestPtr &req) { return process->pTable->translate(req); } - Fault translateDataReadReq(CpuRequestPtr &req) + Fault translateDataReadReq(RequestPtr &req) { return process->pTable->translate(req); } - Fault translateDataWriteReq(CpuRequestPtr &req) + Fault translateDataWriteReq(RequestPtr &req) { return process->pTable->translate(req); } @@ -279,7 +292,7 @@ class CPUExecContext /* template <class T> - Fault read(CpuRequestPtr &req, T &data) + Fault read(RequestPtr &req, T &data) { #if FULL_SYSTEM && THE_ISA == ALPHA_ISA if (req->flags & LOCKED) { @@ -295,7 +308,7 @@ class CPUExecContext } template <class T> - Fault write(CpuRequestPtr &req, T &data) + Fault write(RequestPtr &req, T &data) { #if FULL_SYSTEM && THE_ISA == ALPHA_ISA ExecContext *xc; @@ -356,7 +369,7 @@ class CPUExecContext inst = new_inst; } - Fault instRead(CpuRequestPtr &req) + Fault instRead(RequestPtr &req) { panic("instRead not implemented"); // return funcPhysMem->read(req, inst); @@ -374,103 +387,103 @@ class CPUExecContext // uint64_t readIntReg(int reg_idx) { - return regs.intRegFile[reg_idx]; + return regs.readIntReg(reg_idx); } FloatReg readFloatReg(int reg_idx, int width) { - return regs.floatRegFile.readReg(reg_idx, width); + return regs.readFloatReg(reg_idx, width); } FloatReg readFloatReg(int reg_idx) { - return regs.floatRegFile.readReg(reg_idx); + return regs.readFloatReg(reg_idx); } FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.floatRegFile.readRegBits(reg_idx, width); + return regs.readFloatRegBits(reg_idx, width); } FloatRegBits readFloatRegBits(int reg_idx) { - return regs.floatRegFile.readRegBits(reg_idx); + return regs.readFloatRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) { - regs.intRegFile[reg_idx] = val; + regs.setIntReg(reg_idx, val); } void setFloatReg(int reg_idx, FloatReg val, int width) { - regs.floatRegFile.setReg(reg_idx, val, width); + regs.setFloatReg(reg_idx, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - regs.floatRegFile.setReg(reg_idx, val); + regs.setFloatReg(reg_idx, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.floatRegFile.setRegBits(reg_idx, val, width); + regs.setFloatRegBits(reg_idx, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.floatRegFile.setRegBits(reg_idx, val); + regs.setFloatRegBits(reg_idx, val); } uint64_t readPC() { - return regs.pc; + return regs.readPC(); } void setPC(uint64_t val) { - regs.pc = val; + regs.setPC(val); } uint64_t readNextPC() { - return regs.npc; + return regs.readNextPC(); } void setNextPC(uint64_t val) { - regs.npc = val; + regs.setNextPC(val); } uint64_t readNextNPC() { - return regs.nnpc; + return regs.readNextNPC(); } void setNextNPC(uint64_t val) { - regs.nnpc = val; + regs.setNextNPC(val); } MiscReg readMiscReg(int misc_reg) { - return regs.miscRegs.readReg(misc_reg); + return regs.readMiscReg(misc_reg); } MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { - return regs.miscRegs.readRegWithEffect(misc_reg, fault, proxy); + return regs.readMiscRegWithEffect(misc_reg, fault, proxy); } Fault setMiscReg(int misc_reg, const MiscReg &val) { - return regs.miscRegs.setReg(misc_reg, val); + return regs.setMiscReg(misc_reg, val); } Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return regs.miscRegs.setRegWithEffect(misc_reg, val, proxy); + return regs.setMiscRegWithEffect(misc_reg, val, proxy); } unsigned readStCondFailures() { return storeCondFailures; } @@ -478,26 +491,26 @@ class CPUExecContext void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } - void clearArchRegs() { memset(®s, 0, sizeof(regs)); } + void clearArchRegs() { regs.clear(); } #if FULL_SYSTEM int readIntrFlag() { return regs.intrflag; } void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); - bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } + bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); } bool simPalCheck(int palFunc); #endif #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { - return regs.intRegFile[TheISA::ArgumentReg0 + i]; + return regs.readIntReg(TheISA::ArgumentReg0 + i); } // used to shift args for indirect syscall void setSyscallArg(int i, TheISA::IntReg val) { - regs.intRegFile[TheISA::ArgumentReg0 + i] = val; + regs.setIntReg(TheISA::ArgumentReg0 + i, val); } void setSyscallReturn(SyscallReturn return_value) @@ -514,6 +527,12 @@ class CPUExecContext void setFuncExeInst(Counter new_val) { func_exe_inst = new_val; } #endif + + void changeRegFileContext(RegFile::ContextParam param, + RegFile::ContextVal val) + { + regs.changeContext(param, val); + } }; diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 2fdb19c73..9404b126b 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -36,15 +36,15 @@ #include "sim/serialize.hh" #include "sim/byteswap.hh" -// forward declaration: see functional_memory.hh // @todo: Figure out a more architecture independent way to obtain the ITB and // DTB pointers. class AlphaDTB; class AlphaITB; class BaseCPU; class Event; -class PhysicalMemory; class TranslatingPort; +class FunctionalPort; +class VirtualPort; class Process; class System; @@ -83,8 +83,6 @@ class ExecContext virtual ~ExecContext() { }; - virtual TranslatingPort *getMemPort() = 0; - virtual BaseCPU *getCpuPtr() = 0; virtual void setCpuId(int id) = 0; @@ -94,12 +92,18 @@ class ExecContext #if FULL_SYSTEM virtual System *getSystemPtr() = 0; - virtual PhysicalMemory *getPhysMemPtr() = 0; - virtual AlphaITB *getITBPtr() = 0; virtual AlphaDTB * getDTBPtr() = 0; + + virtual FunctionalPort *getPhysPort() = 0; + + virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; + + virtual void delVirtPort(VirtualPort *vp) = 0; #else + virtual TranslatingPort *getMemPort() = 0; + virtual Process *getProcessPtr() = 0; #endif @@ -148,11 +152,11 @@ class ExecContext virtual int getInstAsid() = 0; virtual int getDataAsid() = 0; - virtual Fault translateInstReq(CpuRequestPtr &req) = 0; + virtual Fault translateInstReq(RequestPtr &req) = 0; - virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0; + virtual Fault translateDataReadReq(RequestPtr &req) = 0; - virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0; + virtual Fault translateDataWriteReq(RequestPtr &req) = 0; // Also somewhat obnoxious. Really only used for the TLB fault. // However, may be quite useful in SPARC. @@ -237,6 +241,9 @@ class ExecContext virtual void setFuncExeInst(Counter new_val) = 0; #endif + + virtual void changeRegFileContext(RegFile::ContextParam param, + RegFile::ContextVal val) = 0; }; template <class XC> @@ -251,8 +258,6 @@ class ProxyExecContext : public ExecContext public: - TranslatingPort *getMemPort() { return actualXC->getMemPort(); } - BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } void setCpuId(int id) { actualXC->setCpuId(id); } @@ -262,12 +267,18 @@ class ProxyExecContext : public ExecContext #if FULL_SYSTEM System *getSystemPtr() { return actualXC->getSystemPtr(); } - PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); } - AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } + + FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } + + VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } + + void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } #else + TranslatingPort *getMemPort() { return actualXC->getMemPort(); } + Process *getProcessPtr() { return actualXC->getProcessPtr(); } #endif @@ -316,13 +327,13 @@ class ProxyExecContext : public ExecContext int getInstAsid() { return actualXC->getInstAsid(); } int getDataAsid() { return actualXC->getDataAsid(); } - Fault translateInstReq(CpuRequestPtr &req) + Fault translateInstReq(RequestPtr &req) { return actualXC->translateInstReq(req); } - Fault translateDataReadReq(CpuRequestPtr &req) + Fault translateDataReadReq(RequestPtr &req) { return actualXC->translateDataReadReq(req); } - Fault translateDataWriteReq(CpuRequestPtr &req) + Fault translateDataWriteReq(RequestPtr &req) { return actualXC->translateDataWriteReq(req); } // @todo: Do I need this? @@ -428,6 +439,12 @@ class ProxyExecContext : public ExecContext void setFuncExeInst(Counter new_val) { return actualXC->setFuncExeInst(new_val); } #endif + + void changeRegFileContext(RegFile::ContextParam param, + RegFile::ContextVal val) + { + actualXC->changeRegFileContext(param, val); + } }; #endif diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc index ebb719b2c..0ed3b43c4 100644 --- a/cpu/exetrace.cc +++ b/cpu/exetrace.cc @@ -29,11 +29,12 @@ #include <fstream> #include <iomanip> -#include "sim/param.hh" -#include "cpu/exetrace.hh" #include "base/loader/symtab.hh" #include "cpu/base.hh" +#include "cpu/exetrace.hh" #include "cpu/static_inst.hh" +#include "sim/param.hh" +#include "sim/system.hh" using namespace std; @@ -127,10 +128,11 @@ Trace::InstRecord::dump(ostream &outs) outs << " A=0x" << hex << addr; if (flags[PRINT_INT_REGS] && regs_valid) { - for (int i = 0; i < 32;) + for (int i = 0; i < TheISA::NumIntRegs;) for (int j = i + 1; i <= j; i++) - ccprintf(outs, "r%02d = %#018x%s", i, iregs->regs[i], - ((i == j) ? "\n" : " ")); + ccprintf(outs, "r%02d = %#018x%s", i, + iregs->regs.readReg(i), + ((i == j) ? "\n" : " ")); outs << "\n"; } diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh index 67d042ec8..a26cdc517 100644 --- a/cpu/exetrace.hh +++ b/cpu/exetrace.hh @@ -163,7 +163,7 @@ InstRecord::setRegs(const IntRegFile ®s) if (!iregs) iregs = new iRegFile; - memcpy(&iregs->regs, regs, sizeof(IntRegFile)); + memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); regs_valid = true; } diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index d188074d4..261ed8302 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -64,8 +64,8 @@ #if FULL_SYSTEM #include "base/remote_gdb.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +//#include "mem/functional/memory_control.hh" +//#include "mem/functional/physical.hh" #include "sim/system.hh" #include "arch/tlb.hh" #include "arch/stacktrace.hh" @@ -86,6 +86,15 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) void SimpleCPU::init() { + //Create Memory Ports (conect them up) + Port *mem_dport = mem->getPort(""); + dcachePort.setPeer(mem_dport); + mem_dport->setPeer(&dcachePort); + + Port *mem_iport = mem->getPort(""); + icachePort.setPeer(mem_iport); + mem_iport->setPeer(&icachePort); + BaseCPU::init(); #if FULL_SYSTEM for (int i = 0; i < execContexts.size(); ++i) { @@ -146,48 +155,44 @@ SimpleCPU::CpuPort::recvRetry() } SimpleCPU::SimpleCPU(Params *p) - : BaseCPU(p), icachePort(this), +#if !FULL_SYSTEM + : BaseCPU(p), mem(p->mem), icachePort(this), dcachePort(this), tickEvent(this, p->width), cpuXC(NULL) +#else + : BaseCPU(p), icachePort(this), dcachePort(this), + tickEvent(this, p->width), cpuXC(NULL) +#endif { _status = Idle; - //Create Memory Ports (conect them up) - Port *mem_dport = p->mem->getPort(); - dcachePort.setPeer(mem_dport); - mem_dport->setPeer(&dcachePort); - - Port *mem_iport = p->mem->getPort(); - icachePort.setPeer(mem_iport); - mem_iport->setPeer(&icachePort); - #if FULL_SYSTEM - cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); + cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb); #else - cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0, - &dcachePort); + cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, + /* asid */ 0, mem); #endif // !FULL_SYSTEM xcProxy = cpuXC->getProxy(); #if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE - ifetch_req = new CpuRequest; - ifetch_req->asid = 0; - ifetch_req->size = sizeof(MachInst); + ifetch_req = new Request(true); + ifetch_req->setAsid(0); + ifetch_req->setSize(sizeof(MachInst)); ifetch_pkt = new Packet; ifetch_pkt->cmd = Read; ifetch_pkt->data = (uint8_t *)&inst; ifetch_pkt->req = ifetch_req; ifetch_pkt->size = sizeof(MachInst); - data_read_req = new CpuRequest; - data_read_req->asid = 0; + data_read_req = new Request(true); + data_read_req->setAsid(0); data_read_pkt = new Packet; data_read_pkt->cmd = Read; data_read_pkt->data = new uint8_t[8]; data_read_pkt->req = data_read_req; - data_write_req = new CpuRequest; - data_write_req->asid = 0; + data_write_req = new Request(true); + data_write_req->setAsid(0); data_write_pkt = new Packet; data_write_pkt->cmd = Write; data_write_pkt->req = data_write_req; @@ -488,13 +493,13 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) // memReq->reset(addr, sizeof(T), flags); #if SIMPLE_CPU_MEM_TIMING - CpuRequest *data_read_req = new CpuRequest; + CpuRequest *data_read_req = new Request(true); #endif - data_read_req->vaddr = addr; - data_read_req->size = sizeof(T); - data_read_req->flags = flags; - data_read_req->time = curTick; + data_read_req->setVaddr(addr); + data_read_req->setSize(sizeof(T)); + data_read_req->setFlags(flags); + data_read_req->setTime(curTick); // translate to physical address Fault fault = cpuXC->translateDataReadReq(data_read_req); @@ -507,7 +512,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) data_read_pkt->req = data_read_req; data_read_pkt->data = new uint8_t[8]; #endif - data_read_pkt->addr = data_read_req->paddr; + data_read_pkt->addr = data_read_req->getPaddr(); data_read_pkt->size = sizeof(T); sendDcacheRequest(data_read_pkt); @@ -554,7 +559,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) } */ // This will need a new way to tell if it has a dcache attached. - if (data_read_req->flags & UNCACHEABLE) + if (data_read_req->getFlags() & UNCACHEABLE) recordEvent("Uncached Read"); return fault; @@ -607,10 +612,10 @@ template <class T> Fault SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) { - data_write_req->vaddr = addr; - data_write_req->time = curTick; - data_write_req->size = sizeof(T); - data_write_req->flags = flags; + data_write_req->setVaddr(addr); + data_write_req->setTime(curTick); + data_write_req->setSize(sizeof(T)); + data_write_req->setFlags(flags); // translate to physical address Fault fault = cpuXC->translateDataWriteReq(data_write_req); @@ -625,7 +630,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) #else data_write_pkt->data = (uint8_t *)&data; #endif - data_write_pkt->addr = data_write_req->paddr; + data_write_pkt->addr = data_write_req->getPaddr(); data_write_pkt->size = sizeof(T); sendDcacheRequest(data_write_pkt); @@ -659,7 +664,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) *res = data_write_pkt->result; // This will need a new way to tell if it's hooked up to a cache or not. - if (data_write_req->flags & UNCACHEABLE) + if (data_write_req->getFlags() & UNCACHEABLE) recordEvent("Uncached Write"); // If the write needs to have a fault on the access, consider calling @@ -899,7 +904,7 @@ SimpleCPU::tick() #if FULL_SYSTEM if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() && - status() != IcacheMissComplete) { + status() != IcacheAccessComplete) { int ipl = 0; int summary = 0; checkInterrupts = false; @@ -968,11 +973,11 @@ SimpleCPU::tick() #if SIMPLE_CPU_MEM_TIMING CpuRequest *ifetch_req = new CpuRequest(); - ifetch_req->size = sizeof(MachInst); + ifetch_req->setSize(sizeof(MachInst)); #endif - ifetch_req->vaddr = cpuXC->readPC() & ~3; - ifetch_req->time = curTick; + ifetch_req->setVaddr(cpuXC->readPC() & ~3); + ifetch_req->setTime(curTick); /* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), IFETCH_FLAGS(xc->regs.pc)); @@ -988,7 +993,7 @@ SimpleCPU::tick() ifetch_pkt->req = ifetch_req; ifetch_pkt->size = sizeof(MachInst); #endif - ifetch_pkt->addr = ifetch_req->paddr; + ifetch_pkt->addr = ifetch_req->getPaddr(); sendIcacheRequest(ifetch_pkt); #if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC @@ -1089,7 +1094,7 @@ SimpleCPU::tick() #endif // FULL_SYSTEM } else { -#if THE_ISA != MIPS_ISA +#if THE_ISA == ALPHA_ISA // go to the next instruction cpuXC->setPC(cpuXC->readNextPC()); cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index dc07027f9..11137b6e6 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -105,6 +105,7 @@ class SimpleCPU : public BaseCPU virtual Packet *recvRetry(); }; + MemObject *mem; CpuPort icachePort; CpuPort dcachePort; @@ -209,12 +210,12 @@ class SimpleCPU : public BaseCPU #if SIMPLE_CPU_MEM_TIMING Packet *retry_pkt; #elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE - CpuRequest *ifetch_req; - Packet *ifetch_pkt; - CpuRequest *data_read_req; - Packet *data_read_pkt; - CpuRequest *data_write_req; - Packet *data_write_pkt; + Request *ifetch_req; + Packet *ifetch_pkt; + Request *data_read_req; + Packet *data_read_pkt; + Request *data_write_req; + Packet *data_write_pkt; #endif // Pointer to the sampler that is telling us to switchover. |