5 files changed, 16 insertions, 16 deletions

diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 86314bef1..296717f2a 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -113,7 +113,7 @@ BaseDynInst<Impl>::initVars()
     asid = 0;
 
     // Initialize the fault to be unimplemented opcode.
-    fault = UnimplementedOpcodeFault;
+    fault = new UnimplementedOpcodeFault;
 
     ++instcount;
 
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index b35bcf9e3..ea0aae41f 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -280,7 +280,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
 #endif
 
-        return this->mem->write(req, (T)::htog(data));
+        return this->mem->write(req, (T)htog(data));
     }
 
     template <class T>
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 7ec1ba663..c0ec1fb33 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -280,7 +280,7 @@ AlphaFullCPU<Impl>::hwrei()
     uint64_t *ipr = getIpr();
 
     if (!inPalMode())
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
     this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -329,21 +329,21 @@ AlphaFullCPU<Impl>::trap(Fault fault)
     // miss
     uint64_t PC = this->commit.readCommitPC();
 
-    DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
-    this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
+    DPRINTF(Fault, "Fault %s\n", fault->name());
+    this->recordEvent(csprintf("Fault %s", fault->name()));
 
-//    kernelStats.fault(fault);
+    //kernelStats.fault(fault);
 
-    if (fault == ArithmeticFault)
+    if (fault->isA<ArithmeticFault>())
         panic("Arithmetic traps are unimplemented!");
 
     AlphaISA::InternalProcReg *ipr = getIpr();
 
     // exception restart address - Get the commit PC
-    if (fault != InterruptFault || !inPalMode(PC))
+    if (!fault->isA<InterruptFault>() || !inPalMode(PC))
         ipr[AlphaISA::IPR_EXC_ADDR] = PC;
 
-    if (fault == PalFault || fault == ArithmeticFault /* ||
+    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
         fault == InterruptFault && !PC_PAL(regs.pc) */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index ee7b8858e..7e36a6ead 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -372,12 +372,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
       case TheISA::IPR_DTB_IAP:
       case TheISA::IPR_ITB_IA:
       case TheISA::IPR_ITB_IAP:
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
     }
 
@@ -525,7 +525,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
       case TheISA::IPR_ITB_PTE_TEMP:
       case TheISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
       case TheISA::IPR_HWINT_CLR:
       case TheISA::IPR_SL_XMIT:
@@ -627,7 +627,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 
     // no error...
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 944bdbb0a..a0a37f45a 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -347,7 +347,7 @@ SimpleCPU::copySrcTranslate(Addr src)
     // translate to physical address
     Fault fault = xc->translateDataReadReq(memReq);
 
-    assert(fault != AlignmentFault);
+    assert(!fault->isA<AlignmentFault>());
 
     if (fault == NoFault) {
         xc->copySrcAddr = src;
@@ -382,7 +382,7 @@ SimpleCPU::copy(Addr dest)
     // translate to physical address
     Fault fault = xc->translateDataWriteReq(memReq);
 
-    assert(fault != AlignmentFault);
+    assert(!fault->isA<AlignmentFault>());
 
     if (fault == NoFault) {
         Addr dest_addr = memReq->paddr + offset;
@@ -688,7 +688,7 @@ SimpleCPU::tick()
         if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
             ipr[IPR_ISR] = summary;
             ipr[IPR_INTID] = ipl;
-            xc->ev5_trap(InterruptFault);
+            xc->ev5_trap(new InterruptFault);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                     ipr[IPR_IPLR], ipl, summary);