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-rw-r--r--cpu/cpu_exec_context.cc4
-rw-r--r--cpu/cpu_exec_context.hh54
-rw-r--r--cpu/exec_context.hh9
-rw-r--r--cpu/exetrace.cc7
-rw-r--r--cpu/exetrace.hh2
-rw-r--r--cpu/simple/cpu.cc2
6 files changed, 47 insertions, 31 deletions
diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index e76c13fb0..62419adcf 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -63,7 +63,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
{
proxy = new ProxyExecContext<CPUExecContext>(this);
- memset(&regs, 0, sizeof(RegFile));
+ regs.clear();
if (cpu->params->profile) {
profile = new FunctionProfile(system->kernelSymtab);
@@ -105,7 +105,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
mem_port->setPeer(port);
port->setPeer(mem_port);
- memset(&regs, 0, sizeof(RegFile));
+ regs.clear();
proxy = new ProxyExecContext<CPUExecContext>(this);
}
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 22d2811d0..c74feec68 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -387,103 +387,103 @@ class CPUExecContext
//
uint64_t readIntReg(int reg_idx)
{
- return regs.intRegFile[reg_idx];
+ return regs.readIntReg(reg_idx);
}
FloatReg readFloatReg(int reg_idx, int width)
{
- return regs.floatRegFile.readReg(reg_idx, width);
+ return regs.readFloatReg(reg_idx, width);
}
FloatReg readFloatReg(int reg_idx)
{
- return regs.floatRegFile.readReg(reg_idx);
+ return regs.readFloatReg(reg_idx);
}
FloatRegBits readFloatRegBits(int reg_idx, int width)
{
- return regs.floatRegFile.readRegBits(reg_idx, width);
+ return regs.readFloatRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(int reg_idx)
{
- return regs.floatRegFile.readRegBits(reg_idx);
+ return regs.readFloatRegBits(reg_idx);
}
void setIntReg(int reg_idx, uint64_t val)
{
- regs.intRegFile[reg_idx] = val;
+ regs.setIntReg(reg_idx, val);
}
void setFloatReg(int reg_idx, FloatReg val, int width)
{
- regs.floatRegFile.setReg(reg_idx, val, width);
+ regs.setFloatReg(reg_idx, val, width);
}
void setFloatReg(int reg_idx, FloatReg val)
{
- regs.floatRegFile.setReg(reg_idx, val);
+ regs.setFloatReg(reg_idx, val);
}
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
- regs.floatRegFile.setRegBits(reg_idx, val, width);
+ regs.setFloatRegBits(reg_idx, val, width);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- regs.floatRegFile.setRegBits(reg_idx, val);
+ regs.setFloatRegBits(reg_idx, val);
}
uint64_t readPC()
{
- return regs.pc;
+ return regs.readPC();
}
void setPC(uint64_t val)
{
- regs.pc = val;
+ regs.setPC(val);
}
uint64_t readNextPC()
{
- return regs.npc;
+ return regs.readNextPC();
}
void setNextPC(uint64_t val)
{
- regs.npc = val;
+ regs.setNextPC(val);
}
uint64_t readNextNPC()
{
- return regs.nnpc;
+ return regs.readNextNPC();
}
void setNextNPC(uint64_t val)
{
- regs.nnpc = val;
+ regs.setNextNPC(val);
}
MiscReg readMiscReg(int misc_reg)
{
- return regs.miscRegs.readReg(misc_reg);
+ return regs.readMiscReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
- return regs.miscRegs.readRegWithEffect(misc_reg, fault, proxy);
+ return regs.readMiscRegWithEffect(misc_reg, fault, proxy);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- return regs.miscRegs.setReg(misc_reg, val);
+ return regs.setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- return regs.miscRegs.setRegWithEffect(misc_reg, val, proxy);
+ return regs.setMiscRegWithEffect(misc_reg, val, proxy);
}
unsigned readStCondFailures() { return storeCondFailures; }
@@ -491,26 +491,26 @@ class CPUExecContext
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }
- void clearArchRegs() { memset(&regs, 0, sizeof(regs)); }
+ void clearArchRegs() { regs.clear(); }
#if FULL_SYSTEM
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();
- bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
+ bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
bool simPalCheck(int palFunc);
#endif
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{
- return regs.intRegFile[TheISA::ArgumentReg0 + i];
+ return regs.readIntReg(TheISA::ArgumentReg0 + i);
}
// used to shift args for indirect syscall
void setSyscallArg(int i, TheISA::IntReg val)
{
- regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
+ regs.setIntReg(TheISA::ArgumentReg0 + i, val);
}
void setSyscallReturn(SyscallReturn return_value)
@@ -527,6 +527,12 @@ class CPUExecContext
void setFuncExeInst(Counter new_val) { func_exe_inst = new_val; }
#endif
+
+ void changeRegFileContext(RegFile::ContextParam param,
+ RegFile::ContextVal val)
+ {
+ regs.changeContext(param, val);
+ }
};
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 85e4bfd4a..dd3d2cba1 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -241,6 +241,9 @@ class ExecContext
virtual void setFuncExeInst(Counter new_val) = 0;
#endif
+
+ virtual void changeRegFileContext(RegFile::ContextParam param,
+ RegFile::ContextVal val) = 0;
};
template <class XC>
@@ -436,6 +439,12 @@ class ProxyExecContext : public ExecContext
void setFuncExeInst(Counter new_val)
{ return actualXC->setFuncExeInst(new_val); }
#endif
+
+ void changeRegFileContext(RegFile::ContextParam param,
+ RegFile::ContextVal val)
+ {
+ actualXC->changeRegFileContext(param, val);
+ }
};
#endif
diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc
index 4db72320c..0ed3b43c4 100644
--- a/cpu/exetrace.cc
+++ b/cpu/exetrace.cc
@@ -128,10 +128,11 @@ Trace::InstRecord::dump(ostream &outs)
outs << " A=0x" << hex << addr;
if (flags[PRINT_INT_REGS] && regs_valid) {
- for (int i = 0; i < 32;)
+ for (int i = 0; i < TheISA::NumIntRegs;)
for (int j = i + 1; i <= j; i++)
- ccprintf(outs, "r%02d = %#018x%s", i, iregs->regs[i],
- ((i == j) ? "\n" : " "));
+ ccprintf(outs, "r%02d = %#018x%s", i,
+ iregs->regs.readReg(i),
+ ((i == j) ? "\n" : " "));
outs << "\n";
}
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index 67d042ec8..a26cdc517 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -163,7 +163,7 @@ InstRecord::setRegs(const IntRegFile &regs)
if (!iregs)
iregs = new iRegFile;
- memcpy(&iregs->regs, regs, sizeof(IntRegFile));
+ memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
regs_valid = true;
}
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 049606036..88c99c566 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -1094,7 +1094,7 @@ SimpleCPU::tick()
#endif // FULL_SYSTEM
}
else {
-#if THE_ISA != MIPS_ISA
+#if THE_ISA == ALPHA_ISA
// go to the next instruction
cpuXC->setPC(cpuXC->readNextPC());
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 15:56:08 +0000