summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/SConscript32
-rw-r--r--cpu/base_dyn_inst.cc7
-rw-r--r--cpu/exec_context.cc51
-rw-r--r--cpu/exec_context.hh64
-rw-r--r--cpu/o3/alpha_cpu.hh52
-rw-r--r--cpu/o3/alpha_cpu_builder.cc4
-rw-r--r--cpu/o3/alpha_cpu_impl.hh62
-rw-r--r--cpu/o3/alpha_dyn_inst.hh34
-rw-r--r--cpu/o3/alpha_dyn_inst_impl.hh42
-rw-r--r--cpu/o3/bpred_unit.hh2
-rw-r--r--cpu/o3/comm.hh2
-rw-r--r--cpu/o3/cpu.cc4
-rw-r--r--cpu/o3/cpu.hh6
-rw-r--r--cpu/o3/regfile.hh397
-rw-r--r--cpu/ozone/cpu_impl.hh2
-rw-r--r--cpu/ozone/ea_list.cc2
-rw-r--r--cpu/ozone/ea_list.hh2
-rw-r--r--cpu/profile.hh2
-rw-r--r--cpu/simple/cpu.cc36
-rw-r--r--cpu/simple/cpu.hh27
-rw-r--r--cpu/static_inst.hh2
21 files changed, 258 insertions, 574 deletions
diff --git a/cpu/SConscript b/cpu/SConscript
index dbe174660..af6bab4eb 100644
--- a/cpu/SConscript
+++ b/cpu/SConscript
@@ -32,13 +32,28 @@ import os.path
# Import build environment variable from SConstruct.
Import('env')
+#################################################################
+#
+# Generate StaticInst execute() method signatures.
+#
+# There must be one signature for each CPU model compiled in.
+# Since the set of compiled-in models is flexible, we generate a
+# header containing the appropriate set of signatures on the fly.
+#
+#################################################################
+
+# CPU model-specific data is contained in cpu_models.py
+# Convert to SCons File node to get path handling
models_db = File('cpu_models.py')
+# slurp in contents of file
execfile(models_db.srcnode().abspath)
+# Template for execute() signature.
exec_sig_template = '''
virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
'''
+# Generate header.
def gen_cpu_exec_signatures(target, source, env):
f = open(str(target[0]), 'w')
print >> f, '''
@@ -52,7 +67,22 @@ def gen_cpu_exec_signatures(target, source, env):
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
-env.Command('static_inst_exec_sigs.hh', models_db, gen_cpu_exec_signatures)
+# Generate string that gets printed when header is rebuilt
+def gen_sigs_string(target, source, env):
+ return "Generating static_inst_exec_sigs.hh: " \
+ + ', '.join(env['CPU_MODELS'])
+
+# Add command to generate header to environment.
+env.Command('static_inst_exec_sigs.hh', models_db,
+ Action(gen_cpu_exec_signatures, gen_sigs_string,
+ varlist = ['CPU_MODELS']))
+
+#################################################################
+#
+# Include CPU-model-specific files based on set of models
+# specified in CPU_MODELS build option.
+#
+#################################################################
sources = []
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 86314bef1..5905cdad2 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -36,7 +36,7 @@
#include "base/cprintf.hh"
#include "base/trace.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/faults.hh"
#include "cpu/exetrace.hh"
#include "mem/mem_req.hh"
@@ -45,6 +45,7 @@
#include "cpu/o3/alpha_cpu.hh"
using namespace std;
+using namespace TheISA;
#define NOHASH
#ifndef NOHASH
@@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars()
asid = 0;
// Initialize the fault to be unimplemented opcode.
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
++instcount;
@@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
break;
default:
- fault = MachineCheckFault;
+ fault = genMachineCheckFault();
break;
}
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 9bed3ba47..7dd9bf58d 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -35,12 +35,13 @@
#include "base/callback.hh"
#include "base/cprintf.hh"
#include "base/output.hh"
+#include "base/trace.hh"
#include "cpu/profile.hh"
#include "kern/kernel_stats.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-#include "targetarch/stacktrace.hh"
+#include "arch/stacktrace.hh"
#else
#include "sim/process.hh"
#endif
@@ -53,10 +54,10 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
FunctionalMemory *_mem)
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
- cpu_id(-1), mem(_mem), itb(_itb), dtb(_dtb), system(_sys),
- memctrl(_sys->memctrl), physmem(_sys->physmem),
+ cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
+ dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
kernelBinning(system->kernelBinning), bin(kernelBinning->bin),
- fnbin(kernelBinning->fnbin), profile(NULL),
+ fnbin(kernelBinning->fnbin), profile(NULL), quiesceEvent(this),
func_exe_inst(0), storeCondFailures(0)
{
kernelStats = new Kernel::Statistics(this);
@@ -79,8 +80,8 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
Process *_process, int _asid)
: _status(ExecContext::Unallocated),
- cpu(_cpu), thread_num(_thread_num), cpu_id(-1),
- process(_process), mem(process->getMemory()), asid(_asid),
+ cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
+ lastSuspend(0), process(_process), mem(process->getMemory()), asid(_asid),
func_exe_inst(0), storeCondFailures(0)
{
memset(&regs, 0, sizeof(RegFile));
@@ -109,6 +110,23 @@ ExecContext::dumpFuncProfile()
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
profile->dump(this, *os);
}
+
+ExecContext::EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
+ : Event(&mainEventQueue), xc(_xc)
+{
+}
+
+void
+ExecContext::EndQuiesceEvent::process()
+{
+ xc->activate();
+}
+
+const char*
+ExecContext::EndQuiesceEvent::description()
+{
+ return "End Quiesce Event.";
+}
#endif
void
@@ -143,7 +161,12 @@ ExecContext::serialize(ostream &os)
SERIALIZE_SCALAR(inst);
#if FULL_SYSTEM
+ Tick quiesceEndTick = 0;
+ if (quiesceEvent.scheduled())
+ quiesceEndTick = quiesceEvent.when();
+ SERIALIZE_SCALAR(quiesceEndTick);
kernelStats->serialize(os);
+
#endif
}
@@ -158,6 +181,11 @@ ExecContext::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(inst);
#if FULL_SYSTEM
+ Tick quiesceEndTick;
+ UNSERIALIZE_SCALAR(quiesceEndTick);
+ if (quiesceEndTick)
+ quiesceEvent.schedule(quiesceEndTick);
+
kernelStats->unserialize(cp, section);
#endif
}
@@ -169,6 +197,8 @@ ExecContext::activate(int delay)
if (status() == Active)
return;
+ lastActivate = curTick;
+
_status = Active;
cpu->activateContext(thread_num, delay);
}
@@ -179,6 +209,9 @@ ExecContext::suspend()
if (status() == Suspended)
return;
+ lastActivate = curTick;
+ lastSuspend = curTick;
+/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->check_interrupts()) {
@@ -186,7 +219,7 @@ ExecContext::suspend()
return;
}
#endif
-
+*/
_status = Suspended;
cpu->suspendContext(thread_num);
}
@@ -227,7 +260,7 @@ ExecContext::trap(Fault fault)
/** @todo: Going to hack it for now. Do a true fixup later. */
#if FULL_SYSTEM
- ev5_trap(fault);
+ fault->ev5_trap(this);
#else
fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
#endif
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 3e0d77254..d8ec88537 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -32,6 +32,7 @@
#include "config/full_system.hh"
#include "mem/functional/functional.hh"
#include "mem/mem_req.hh"
+#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
#include "arch/isa_traits.hh"
@@ -46,7 +47,7 @@ class BaseCPU;
#if FULL_SYSTEM
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
+#include "arch/tlb.hh"
class FunctionProfile;
class ProfileNode;
@@ -71,6 +72,7 @@ class ExecContext
typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscRegFile MiscRegFile;
+ typedef TheISA::MiscReg MiscReg;
public:
enum Status
{
@@ -131,6 +133,9 @@ class ExecContext
// it belongs. For full-system mode, this is the system CPU ID.
int cpu_id;
+ Tick lastActivate;
+ Tick lastSuspend;
+
#if FULL_SYSTEM
FunctionalMemory *mem;
AlphaITB *itb;
@@ -153,6 +158,22 @@ class ExecContext
Addr profilePC;
void dumpFuncProfile();
+ /** Event for timing out quiesce instruction */
+ struct EndQuiesceEvent : public Event
+ {
+ /** A pointer to the execution context that is quiesced */
+ ExecContext *xc;
+
+ EndQuiesceEvent(ExecContext *_xc);
+
+ /** Event process to occur at interrupt*/
+ virtual void process();
+
+ /** Event description */
+ virtual const char *description();
+ };
+ EndQuiesceEvent quiesceEvent;
+
#else
Process *process;
@@ -270,8 +291,8 @@ class ExecContext
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
MiscRegFile *cregs = &req->xc->regs.miscRegs;
- cregs->lock_addr = req->paddr;
- cregs->lock_flag = true;
+ cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
+ cregs->setReg(TheISA::Lock_Flag_DepTag, true);
}
#endif
@@ -297,10 +318,12 @@ class ExecContext
req->result = 2;
req->xc->storeCondFailures = 0;//Needed? [RGD]
} else {
- req->result = cregs->lock_flag;
- if (!cregs->lock_flag ||
- ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- cregs->lock_flag = false;
+ bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
+ Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
+ req->result = lock_flag;
+ if (!lock_flag ||
+ ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
+ cregs->setReg(TheISA::Lock_Flag_DepTag, false);
if (((++req->xc->storeCondFailures) % 100000) == 0) {
std::cerr << "Warning: "
<< req->xc->storeCondFailures
@@ -321,8 +344,9 @@ class ExecContext
// through.
for (int i = 0; i < system->execContexts.size(); i++){
cregs = &system->execContexts[i]->regs.miscRegs;
- if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
- cregs->lock_flag = false;
+ if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
+ (req->paddr & ~0xf)) {
+ cregs->setReg(TheISA::Lock_Flag_DepTag, false);
}
}
@@ -398,34 +422,32 @@ class ExecContext
regs.npc = val;
}
- uint64_t readUniq()
+ MiscReg readMiscReg(int misc_reg)
{
- return regs.miscRegs.uniq;
+ return regs.miscRegs.readReg(misc_reg);
}
- void setUniq(uint64_t val)
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
- regs.miscRegs.uniq = val;
+ return regs.miscRegs.readRegWithEffect(misc_reg, fault, this);
}
- uint64_t readFpcr()
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- return regs.miscRegs.fpcr;
+ return regs.miscRegs.setReg(misc_reg, val);
}
- void setFpcr(uint64_t val)
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- regs.miscRegs.fpcr = val;
+ return regs.miscRegs.setRegWithEffect(misc_reg, val, this);
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
- void ev5_trap(Fault fault);
+ void ev5_temp_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index b35bcf9e3..38c00a3a9 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -41,6 +41,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
{
protected:
typedef TheISA::IntReg IntReg;
+ typedef TheISA::MiscReg MiscReg;
+
public:
typedef typename Impl::Params Params;
@@ -111,33 +113,24 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// Later on may want to remove this misc stuff from the regfile and
// have it handled at this level. Might prove to be an issue when
// trying to rename source/destination registers...
- uint64_t readUniq()
- {
- return this->regFile.readUniq();
- }
-
- void setUniq(uint64_t val)
+ MiscReg readMiscReg(int misc_reg)
{
- this->regFile.setUniq(val);
+ // Dummy function for now.
+ // @todo: Fix this once reg file gets fixed.
+ return 0;
}
- uint64_t readFpcr()
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- return this->regFile.readFpcr();
- }
-
- void setFpcr(uint64_t val)
- {
- this->regFile.setFpcr(val);
+ // Dummy function for now.
+ // @todo: Fix this once reg file gets fixed.
+ return NoFault;
}
// Most of the full system code and syscall emulation is not yet
// implemented. These functions do show what the final interface will
// look like.
#if FULL_SYSTEM
- uint64_t *getIpr();
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
int readIntrFlag();
void setIntrFlag(int val);
Fault hwrei();
@@ -216,8 +209,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
MiscRegFile *cregs = &req->xc->regs.miscRegs;
- cregs->lock_addr = req->paddr;
- cregs->lock_flag = true;
+ cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
+ cregs->setReg(TheISA::Lock_Flag_DepTag, true);
}
#endif
@@ -242,22 +235,24 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// If this is a store conditional, act appropriately
if (req->flags & LOCKED) {
- cregs = &this->xc->regs.miscRegs;
+ cregs = &req->xc->regs.miscRegs;
if (req->flags & UNCACHEABLE) {
// Don't update result register (see stq_c in isa_desc)
req->result = 2;
req->xc->storeCondFailures = 0;//Needed? [RGD]
} else {
- req->result = cregs->lock_flag;
- if (!cregs->lock_flag ||
- ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- cregs->lock_flag = false;
+ bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
+ Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
+ req->result = lock_flag;
+ if (!lock_flag ||
+ ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
+ cregs->setReg(TheISA::Lock_Flag_DepTag, false);
if (((++req->xc->storeCondFailures) % 100000) == 0) {
std::cerr << "Warning: "
<< req->xc->storeCondFailures
<< " consecutive store conditional failures "
- << "on cpu " << this->cpu_id
+ << "on cpu " << req->xc->cpu_id
<< std::endl;
}
return NoFault;
@@ -273,14 +268,15 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// through.
for (int i = 0; i < this->system->execContexts.size(); i++){
cregs = &this->system->execContexts[i]->regs.miscRegs;
- if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
- cregs->lock_flag = false;
+ if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
+ (req->paddr & ~0xf)) {
+ cregs->setReg(TheISA::Lock_Flag_DepTag, false);
}
}
#endif
- return this->mem->write(req, (T)::htog(data));
+ return this->mem->write(req, (T)htog(data));
}
template <class T>
diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 3547fb1b5..95d2f8f37 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -50,8 +50,8 @@
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/tlb.hh"
+#include "arch/vtophys.hh"
#else // !FULL_SYSTEM
#include "mem/functional/functional.hh"
#endif // FULL_SYSTEM
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 7ec1ba663..daa61bb1c 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -179,12 +179,12 @@ AlphaFullCPU<Impl>::copyToXC()
this->xc->regs.floatRegFile.q[i] =
this->regFile.readFloatRegInt(renamed_reg);
}
-
+/*
this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
-
+*/
this->xc->regs.pc = this->rob.readHeadPC();
this->xc->regs.npc = this->xc->regs.pc+4;
@@ -221,13 +221,13 @@ AlphaFullCPU<Impl>::copyFromXC()
this->regFile.setFloatRegInt(renamed_reg,
this->xc->regs.floatRegFile.q[i]);
}
-
+ /*
// Then loop through the misc registers.
this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
-
+ */
// Then finally set the PC and the next PC.
// regFile.pc = xc->regs.pc;
// regFile.npc = xc->regs.npc;
@@ -238,27 +238,6 @@ AlphaFullCPU<Impl>::copyFromXC()
#if FULL_SYSTEM
template <class Impl>
-uint64_t *
-AlphaFullCPU<Impl>::getIpr()
-{
- return this->regFile.getIpr();
-}
-
-template <class Impl>
-uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
-{
- return this->regFile.readIpr(idx, fault);
-}
-
-template <class Impl>
-Fault
-AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
-{
- return this->regFile.setIpr(idx, val);
-}
-
-template <class Impl>
int
AlphaFullCPU<Impl>::readIntrFlag()
{
@@ -277,16 +256,14 @@ template <class Impl>
Fault
AlphaFullCPU<Impl>::hwrei()
{
- uint64_t *ipr = getIpr();
-
if (!inPalMode())
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
- this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+ this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
// kernelStats.hwrei();
- if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
+ if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
// AlphaISA::swap_palshadow(&regs, false);
this->checkInterrupts = true;
@@ -329,31 +306,32 @@ AlphaFullCPU<Impl>::trap(Fault fault)
// miss
uint64_t PC = this->commit.readCommitPC();
- DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
- this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
+ DPRINTF(Fault, "Fault %s\n", fault->name());
+ this->recordEvent(csprintf("Fault %s", fault->name()));
-// kernelStats.fault(fault);
+ //kernelStats.fault(fault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
- AlphaISA::InternalProcReg *ipr = getIpr();
-
// exception restart address - Get the commit PC
- if (fault != InterruptFault || !inPalMode(PC))
- ipr[AlphaISA::IPR_EXC_ADDR] = PC;
+ if (!fault->isA<InterruptFault>() || !inPalMode(PC))
+ this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
- if (fault == PalFault || fault == ArithmeticFault /* ||
+ if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
- ipr[AlphaISA::IPR_EXC_ADDR] += 4;
+ AlphaISA::MiscReg ipr_exc_addr =
+ this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
+ this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
+ ipr_exc_addr + 4);
}
if (!inPalMode(PC))
swapPALShadow(true);
- this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
- AlphaISA::fault_addr(fault) );
+ this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect());
this->regFile.setNextPC(PC + sizeof(MachInst));
}
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index f282c287c..e7f7d3a57 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -54,6 +54,8 @@ class AlphaDynInst : public BaseDynInst<Impl>
typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */
typedef TheISA::IntReg IntReg;
+ /** Misc register index type. */
+ typedef TheISA::MiscReg MiscReg;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
@@ -75,15 +77,35 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
- uint64_t readUniq();
- void setUniq(uint64_t val);
+ MiscReg readMiscReg(int misc_reg)
+ {
+ // Dummy function for now.
+ // @todo: Fix this once reg file gets fixed.
+ return 0;
+ }
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ {
+ // Dummy function for now.
+ // @todo: Fix this once reg file gets fixed.
+ return 0;
+ }
- uint64_t readFpcr();
- void setFpcr(uint64_t val);
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ {
+ // Dummy function for now.
+ // @todo: Fix this once reg file gets fixed.
+ return NoFault;
+ }
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ {
+ // Dummy function for now.
+ // @todo: Fix this once reg file gets fixed.
+ return NoFault;
+ }
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
Fault hwrei();
int readIntrFlag();
void setIntrFlag(int val);
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index eebe7675a..96b7d3430 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -67,50 +67,8 @@ AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
}
}
-template <class Impl>
-uint64_t
-AlphaDynInst<Impl>::readUniq()
-{
- return this->cpu->readUniq();
-}
-
-template <class Impl>
-void
-AlphaDynInst<Impl>::setUniq(uint64_t val)
-{
- this->cpu->setUniq(val);
-}
-
-template <class Impl>
-uint64_t
-AlphaDynInst<Impl>::readFpcr()
-{
- return this->cpu->readFpcr();
-}
-
-template <class Impl>
-void
-AlphaDynInst<Impl>::setFpcr(uint64_t val)
-{
- this->cpu->setFpcr(val);
-}
-
#if FULL_SYSTEM
template <class Impl>
-uint64_t
-AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
-{
- return this->cpu->readIpr(idx, fault);
-}
-
-template <class Impl>
-Fault
-AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
-{
- return this->cpu->setIpr(idx, val);
-}
-
-template <class Impl>
Fault
AlphaDynInst<Impl>::hwrei()
{
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 0a77b83dc..2725684f7 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -30,7 +30,7 @@
#define __BPRED_UNIT_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh
index e4de1d304..c74c77ddf 100644
--- a/cpu/o3/comm.hh
+++ b/cpu/o3/comm.hh
@@ -31,7 +31,7 @@
#include <vector>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
#include "sim/host.hh"
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index 706657887..a8c620028 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -264,13 +264,13 @@ FullO3CPU<Impl>::init()
regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
}
-
+/*
// Then loop through the misc registers.
regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr;
regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq;
regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag;
regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr;
-
+*/
// Then finally set the PC and the next PC.
regFile.pc = src_xc->regs.pc;
regFile.npc = src_xc->regs.npc;
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 321d61dce..02908887e 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -50,7 +50,7 @@
#include "sim/process.hh"
#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
+#include "arch/ev5.hh"
using namespace EV5;
#endif
@@ -152,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
/** Get instruction asid. */
int getInstAsid()
- { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
+ { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); }
/** Get data asid. */
int getDataAsid()
- { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
+ { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); }
#else
bool validInstAddr(Addr addr)
{ return thread[0]->validInstAddr(addr); }
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index ee7b8858e..691a75382 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -31,14 +31,14 @@
// @todo: Destructor
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
+#include "arch/ev5.hh"
#include "kern/kernel_stats.hh"
using namespace EV5;
@@ -56,6 +56,8 @@ class PhysRegFile
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::MiscRegFile MiscRegFile;
+ typedef TheISA::MiscReg MiscReg;
+
//Note that most of the definitions of the IntReg, FloatReg, etc. exist
//within the Impl/ISA class and not within this PhysRegFile class.
@@ -194,30 +196,21 @@ class PhysRegFile
//Consider leaving this stuff and below in some implementation specific
//file as opposed to the general register file. Or have a derived class.
- uint64_t readUniq()
- {
- return miscRegs.uniq;
- }
-
- void setUniq(uint64_t val)
- {
- miscRegs.uniq = val;
- }
-
- uint64_t readFpcr()
+ MiscReg readMiscReg(int misc_reg)
{
- return miscRegs.fpcr;
+ // Dummy function for now.
+ // @todo: Fix this once proxy XC is used.
+ return 0;
}
- void setFpcr(uint64_t val)
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- miscRegs.fpcr = val;
+ // Dummy function for now.
+ // @todo: Fix this once proxy XC is used.
+ return NoFault;
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
- InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
#endif
@@ -272,368 +265,4 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
memset(floatRegFile, 0, sizeof(*floatRegFile));
}
-#if FULL_SYSTEM
-
-//Problem: This code doesn't make sense at the RegFile level because it
-//needs things such as the itb and dtb. Either put it at the CPU level or
-//the DynInst level.
-template <class Impl>
-uint64_t
-PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
-{
- uint64_t retval = 0; // return value, default 0
-
- switch (idx) {
- case TheISA::IPR_PALtemp0:
- case TheISA::IPR_PALtemp1:
- case TheISA::IPR_PALtemp2:
- case TheISA::IPR_PALtemp3:
- case TheISA::IPR_PALtemp4:
- case TheISA::IPR_PALtemp5:
- case TheISA::IPR_PALtemp6:
- case TheISA::IPR_PALtemp7:
- case TheISA::IPR_PALtemp8:
- case TheISA::IPR_PALtemp9:
- case TheISA::IPR_PALtemp10:
- case TheISA::IPR_PALtemp11:
- case TheISA::IPR_PALtemp12:
- case TheISA::IPR_PALtemp13:
- case TheISA::IPR_PALtemp14:
- case TheISA::IPR_PALtemp15:
- case TheISA::IPR_PALtemp16:
- case TheISA::IPR_PALtemp17:
- case TheISA::IPR_PALtemp18:
- case TheISA::IPR_PALtemp19:
- case TheISA::IPR_PALtemp20:
- case TheISA::IPR_PALtemp21:
- case TheISA::IPR_PALtemp22:
- case TheISA::IPR_PALtemp23:
- case TheISA::IPR_PAL_BASE:
-
- case TheISA::IPR_IVPTBR:
- case TheISA::IPR_DC_MODE:
- case TheISA::IPR_MAF_MODE:
- case TheISA::IPR_ISR:
- case TheISA::IPR_EXC_ADDR:
- case TheISA::IPR_IC_PERR_STAT:
- case TheISA::IPR_DC_PERR_STAT:
- case TheISA::IPR_MCSR:
- case TheISA::IPR_ASTRR:
- case TheISA::IPR_ASTER:
- case TheISA::IPR_SIRR:
- case TheISA::IPR_ICSR:
- case TheISA::IPR_ICM:
- case TheISA::IPR_DTB_CM:
- case TheISA::IPR_IPLR:
- case TheISA::IPR_INTID:
- case TheISA::IPR_PMCTR:
- // no side-effect
- retval = ipr[idx];
- break;
-
- case TheISA::IPR_CC:
- retval |= ipr[idx] & ULL(0xffffffff00000000);
- retval |= curTick & ULL(0x00000000ffffffff);
- break;
-
- case TheISA::IPR_VA:
- retval = ipr[idx];
- break;
-
- case TheISA::IPR_VA_FORM:
- case TheISA::IPR_MM_STAT:
- case TheISA::IPR_IFAULT_VA_FORM:
- case TheISA::IPR_EXC_MASK:
- case TheISA::IPR_EXC_SUM:
- retval = ipr[idx];
- break;
-
- case TheISA::IPR_DTB_PTE:
- {
- TheISA::PTE &pte = cpu->dtb->index(1);
-
- retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
- retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
- retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
- retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
- retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
- retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
- retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
- }
- break;
-
- // write only registers
- case TheISA::IPR_HWINT_CLR:
- case TheISA::IPR_SL_XMIT:
- case TheISA::IPR_DC_FLUSH:
- case TheISA::IPR_IC_FLUSH:
- case TheISA::IPR_ALT_MODE:
- case TheISA::IPR_DTB_IA:
- case TheISA::IPR_DTB_IAP:
- case TheISA::IPR_ITB_IA:
- case TheISA::IPR_ITB_IAP:
- fault = UnimplementedOpcodeFault;
- break;
-
- default:
- // invalid IPR
- fault = UnimplementedOpcodeFault;
- break;
- }
-
- return retval;
-}
-
-extern int break_ipl;
-
-template <class Impl>
-Fault
-PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
-{
- uint64_t old;
-
- switch (idx) {
- case TheISA::IPR_PALtemp0:
- case TheISA::IPR_PALtemp1:
- case TheISA::IPR_PALtemp2:
- case TheISA::IPR_PALtemp3:
- case TheISA::IPR_PALtemp4:
- case TheISA::IPR_PALtemp5:
- case TheISA::IPR_PALtemp6:
- case TheISA::IPR_PALtemp7:
- case TheISA::IPR_PALtemp8:
- case TheISA::IPR_PALtemp9:
- case TheISA::IPR_PALtemp10:
- case TheISA::IPR_PALtemp11:
- case TheISA::IPR_PALtemp12:
- case TheISA::IPR_PALtemp13:
- case TheISA::IPR_PALtemp14:
- case TheISA::IPR_PALtemp15:
- case TheISA::IPR_PALtemp16:
- case TheISA::IPR_PALtemp17:
- case TheISA::IPR_PALtemp18:
- case TheISA::IPR_PALtemp19:
- case TheISA::IPR_PALtemp20:
- case TheISA::IPR_PALtemp21:
- case TheISA::IPR_PALtemp22:
- case TheISA::IPR_PAL_BASE:
- case TheISA::IPR_IC_PERR_STAT:
- case TheISA::IPR_DC_PERR_STAT:
- case TheISA::IPR_PMCTR:
- // write entire quad w/ no side-effect
- ipr[idx] = val;
- break;
-
- case TheISA::IPR_CC_CTL:
- // This IPR resets the cycle counter. We assume this only
- // happens once... let's verify that.
- assert(ipr[idx] == 0);
- ipr[idx] = 1;
- break;
-
- case TheISA::IPR_CC:
- // This IPR only writes the upper 64 bits. It's ok to write
- // all 64 here since we mask out the lower 32 in rpcc (see
- // isa_desc).
- ipr[idx] = val;
- break;
-
- case TheISA::IPR_PALtemp23:
- // write entire quad w/ no side-effect
- old = ipr[idx];
- ipr[idx] = val;
- break;
-
- case TheISA::IPR_DTB_PTE:
- // write entire quad w/ no side-effect, tag is forthcoming
- ipr[idx] = val;
- break;
-
- case TheISA::IPR_EXC_ADDR:
- // second least significant bit in PC is always zero
- ipr[idx] = val & ~2;
- break;
-
- case TheISA::IPR_ASTRR:
- case TheISA::IPR_ASTER:
- // only write least significant four bits - privilege mask
- ipr[idx] = val & 0xf;
- break;
-
- case TheISA::IPR_IPLR:
- // only write least significant five bits - interrupt level
- ipr[idx] = val & 0x1f;
- break;
-
- case TheISA::IPR_DTB_CM:
-
- case TheISA::IPR_ICM:
- // only write two mode bits - processor mode
- ipr[idx] = val & 0x18;
- break;
-
- case TheISA::IPR_ALT_MODE:
- // only write two mode bits - processor mode
- ipr[idx] = val & 0x18;
- break;
-
- case TheISA::IPR_MCSR:
- // more here after optimization...
- ipr[idx] = val;
- break;
-
- case TheISA::IPR_SIRR:
- // only write software interrupt mask
- ipr[idx] = val & 0x7fff0;
- break;
-
- case TheISA::IPR_ICSR:
- ipr[idx] = val & ULL(0xffffff0300);
- break;
-
- case TheISA::IPR_IVPTBR:
- case TheISA::IPR_MVPTBR:
- ipr[idx] = val & ULL(0xffffffffc0000000);
- break;
-
- case TheISA::IPR_DC_TEST_CTL:
- ipr[idx] = val & 0x1ffb;
- break;
-
- case TheISA::IPR_DC_MODE:
- case TheISA::IPR_MAF_MODE:
- ipr[idx] = val & 0x3f;
- break;
-
- case TheISA::IPR_ITB_ASN:
- ipr[idx] = val & 0x7f0;
- break;
-
- case TheISA::IPR_DTB_ASN:
- ipr[idx] = val & ULL(0xfe00000000000000);
- break;
-
- case TheISA::IPR_EXC_SUM:
- case TheISA::IPR_EXC_MASK:
- // any write to this register clears it
- ipr[idx] = 0;
- break;
-
- case TheISA::IPR_INTID:
- case TheISA::IPR_SL_RCV:
- case TheISA::IPR_MM_STAT:
- case TheISA::IPR_ITB_PTE_TEMP:
- case TheISA::IPR_DTB_PTE_TEMP:
- // read-only registers
- return UnimplementedOpcodeFault;
-
- case TheISA::IPR_HWINT_CLR:
- case TheISA::IPR_SL_XMIT:
- case TheISA::IPR_DC_FLUSH:
- case TheISA::IPR_IC_FLUSH:
- // the following are write only
- ipr[idx] = val;
- break;
-
- case TheISA::IPR_DTB_IA:
- // really a control write
- ipr[idx] = 0;
-
- cpu->dtb->flushAll();
- break;
-
- case TheISA::IPR_DTB_IAP:
- // really a control write
- ipr[idx] = 0;
-
- cpu->dtb->flushProcesses();
- break;
-
- case TheISA::IPR_DTB_IS:
- // really a control write
- ipr[idx] = val;
-
- cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
- break;
-
- case TheISA::IPR_DTB_TAG: {
- struct TheISA::PTE pte;
-
- // FIXME: granularity hints NYI...
- if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
- panic("PTE GH field != 0");
-
- // write entire quad
- ipr[idx] = val;
-
- // construct PTE for new entry
- pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
- pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
- pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
- pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
- pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
- pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
- pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
-
- // insert new TAG/PTE value into data TLB
- cpu->dtb->insert(val, pte);
- }
- break;
-
- case TheISA::IPR_ITB_PTE: {
- struct TheISA::PTE pte;
-
- // FIXME: granularity hints NYI...
- if (ITB_PTE_GH(val) != 0)
- panic("PTE GH field != 0");
-
- // write entire quad
- ipr[idx] = val;
-
- // construct PTE for new entry
- pte.ppn = ITB_PTE_PPN(val);
- pte.xre = ITB_PTE_XRE(val);
- pte.xwe = 0;
- pte.fonr = ITB_PTE_FONR(val);
- pte.fonw = ITB_PTE_FONW(val);
- pte.asma = ITB_PTE_ASMA(val);
- pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
-
- // insert new TAG/PTE value into data TLB
- cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
- }
- break;
-
- case TheISA::IPR_ITB_IA:
- // really a control write
- ipr[idx] = 0;
-
- cpu->itb->flushAll();
- break;
-
- case TheISA::IPR_ITB_IAP:
- // really a control write
- ipr[idx] = 0;
-
- cpu->itb->flushProcesses();
- break;
-
- case TheISA::IPR_ITB_IS:
- // really a control write
- ipr[idx] = val;
-
- cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
- break;
-
- default:
- // invalid IPR
- return UnimplementedOpcodeFault;
- }
-
- // no error...
- return NoFault;
-}
-
-#endif // #if FULL_SYSTEM
-
#endif // __CPU_O3_CPU_REGFILE_HH__
diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh
index 009a81b98..e7ed3cfe0 100644
--- a/cpu/ozone/cpu_impl.hh
+++ b/cpu/ozone/cpu_impl.hh
@@ -29,7 +29,7 @@
#ifndef __CPU_OOO_CPU_OOO_IMPL_HH__
#define __CPU_OOO_CPU_OOO_IMPL_HH__
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
template <class Impl>
class OoOCPU;
diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc
index 80cf80fb8..6114a0ca1 100644
--- a/cpu/ozone/ea_list.cc
+++ b/cpu/ozone/ea_list.cc
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ooo_cpu/ea_list.hh"
diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh
index def7e67d5..c0eee4bb8 100644
--- a/cpu/ozone/ea_list.hh
+++ b/cpu/ozone/ea_list.hh
@@ -32,7 +32,7 @@
#include <list>
#include <utility>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
/**
diff --git a/cpu/profile.hh b/cpu/profile.hh
index 18061f9bf..1eb012a27 100644
--- a/cpu/profile.hh
+++ b/cpu/profile.hh
@@ -33,7 +33,7 @@
#include "cpu/static_inst.hh"
#include "sim/host.hh"
-#include "targetarch/stacktrace.hh"
+#include "arch/stacktrace.hh"
class ProfileNode
{
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 944bdbb0a..ca5d54694 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -67,9 +67,9 @@
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/stacktrace.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/tlb.hh"
+#include "arch/stacktrace.hh"
+#include "arch/vtophys.hh"
#else // !FULL_SYSTEM
#include "mem/functional/functional.hh"
#endif // FULL_SYSTEM
@@ -347,12 +347,12 @@ SimpleCPU::copySrcTranslate(Addr src)
// translate to physical address
Fault fault = xc->translateDataReadReq(memReq);
- assert(fault != AlignmentFault);
-
if (fault == NoFault) {
xc->copySrcAddr = src;
xc->copySrcPhysAddr = memReq->paddr + offset;
} else {
+ assert(!fault->isAlignmentFault());
+
xc->copySrcAddr = 0;
xc->copySrcPhysAddr = 0;
}
@@ -382,8 +382,6 @@ SimpleCPU::copy(Addr dest)
// translate to physical address
Fault fault = xc->translateDataWriteReq(memReq);
- assert(fault != AlignmentFault);
-
if (fault == NoFault) {
Addr dest_addr = memReq->paddr + offset;
// Need to read straight from memory since we have more than 8 bytes.
@@ -402,6 +400,9 @@ SimpleCPU::copy(Addr dest)
dcacheInterface->access(memReq);
}
}
+ else
+ assert(!fault->isAlignmentFault());
+
return fault;
}
@@ -659,12 +660,11 @@ SimpleCPU::tick()
int ipl = 0;
int summary = 0;
checkInterrupts = false;
- IntReg *ipr = xc->regs.ipr;
- if (xc->regs.ipr[IPR_SIRR]) {
+ if (xc->readMiscReg(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+ if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
@@ -682,16 +682,16 @@ SimpleCPU::tick()
}
}
- if (ipr[IPR_ASTRR])
+ if (xc->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
- if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
- ipr[IPR_ISR] = summary;
- ipr[IPR_INTID] = ipl;
- xc->ev5_trap(InterruptFault);
+ if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) {
+ xc->setMiscReg(IPR_ISR, summary);
+ xc->setMiscReg(IPR_INTID, ipl);
+ (new InterruptFault)->ev5_trap(xc);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- ipr[IPR_IPLR], ipl, summary);
+ xc->readMiscReg(IPR_IPLR), ipl, summary);
}
}
#endif
@@ -782,7 +782,7 @@ SimpleCPU::tick()
}
if (xc->profile) {
- bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
+ bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
xc->profilePC = usermode ? 1 : xc->regs.pc;
ProfileNode *node = xc->profile->consume(xc, inst);
if (node)
@@ -812,7 +812,7 @@ SimpleCPU::tick()
if (fault != NoFault) {
#if FULL_SYSTEM
- xc->ev5_trap(fault);
+ fault->ev5_trap(xc);
#else // !FULL_SYSTEM
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
#endif // FULL_SYSTEM
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index ed7b1e29b..243172821 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -65,6 +65,7 @@ class SimpleCPU : public BaseCPU
{
protected:
typedef TheISA::MachInst MachInst;
+ typedef TheISA::MiscReg MiscReg;
public:
// main simulation loop (one cycle)
void tick();
@@ -321,20 +322,32 @@ class SimpleCPU : public BaseCPU
uint64_t readPC() { return xc->readPC(); }
void setNextPC(uint64_t val) { xc->setNextPC(val); }
- uint64_t readUniq() { return xc->readUniq(); }
- void setUniq(uint64_t val) { xc->setUniq(val); }
+ MiscReg readMiscReg(int misc_reg)
+ {
+ return xc->readMiscReg(misc_reg);
+ }
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ {
+ return xc->readMiscRegWithEffect(misc_reg, fault);
+ }
- uint64_t readFpcr() { return xc->readFpcr(); }
- void setFpcr(uint64_t val) { xc->setFpcr(val); }
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ {
+ return xc->setMiscReg(misc_reg, val);
+ }
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ {
+ return xc->setMiscRegWithEffect(misc_reg, val);
+ }
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
- Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
- void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
+ void ev5_trap(Fault fault) { fault->ev5_trap(xc); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index a0287a2de..5566f2f6d 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -109,6 +109,8 @@ class StaticInstBase : public RefCounted
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
+ IsCondDelaySlot,///< Conditional Delay-Slot Instruction
+
IsThreadSync, ///< Thread synchronization operation.
IsSerializing, ///< Serializes pipeline: won't execute until all
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 21:56:42 +0000