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-rw-r--r--cpu/simple_cpu/simple_cpu.cc59
-rw-r--r--cpu/simple_cpu/simple_cpu.hh59
2 files changed, 62 insertions, 56 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 8b99a0105..77f0c41ed 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -216,6 +216,63 @@ SimpleCPU::execCtxStatusChg(int thread_num) {
setStatus(Idle);
}
+void
+SimpleCPU::setStatus(Status new_status)
+{
+ Status old_status = status();
+
+ // We should never even get here if the CPU has been switched out.
+ assert(old_status != SwitchedOut);
+
+ _status = new_status;
+
+ switch (status()) {
+ case IcacheMissStall:
+ assert(old_status == Running);
+ lastIcacheStall = curTick;
+ if (tickEvent.scheduled())
+ tickEvent.squash();
+ break;
+
+ case IcacheMissComplete:
+ assert(old_status == IcacheMissStall);
+ if (tickEvent.squashed())
+ tickEvent.reschedule(curTick + 1);
+ else if (!tickEvent.scheduled())
+ tickEvent.schedule(curTick + 1);
+ break;
+
+ case DcacheMissStall:
+ assert(old_status == Running);
+ lastDcacheStall = curTick;
+ if (tickEvent.scheduled())
+ tickEvent.squash();
+ break;
+
+ case Idle:
+ assert(old_status == Running);
+ notIdleFraction--;
+ if (tickEvent.scheduled())
+ tickEvent.squash();
+ break;
+
+ case Running:
+ assert(old_status == Idle ||
+ old_status == DcacheMissStall ||
+ old_status == IcacheMissComplete);
+ if (old_status == Idle)
+ notIdleFraction++;
+
+ if (tickEvent.squashed())
+ tickEvent.reschedule(curTick + 1);
+ else if (!tickEvent.scheduled())
+ tickEvent.schedule(curTick + 1);
+ break;
+
+ default:
+ panic("can't get here");
+ }
+}
void
SimpleCPU::regStats()
@@ -251,6 +308,7 @@ SimpleCPU::regStats()
.prereq(dcacheStallCycles)
;
+ idleFraction = constant(1.0) - notIdleFraction;
numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
simInsts += numInsts;
}
@@ -259,6 +317,7 @@ void
SimpleCPU::resetStats()
{
startNumInst = numInst;
+ notIdleFraction = (_status != Idle);
}
void
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index b0189349f..666fe490b 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -174,61 +174,7 @@ class SimpleCPU : public BaseCPU
virtual void execCtxStatusChg(int thread_num);
- void setStatus(Status new_status) {
- Status old_status = status();
-
- // We should never even get here if the CPU has been switched out.
- assert(old_status != SwitchedOut);
-
- _status = new_status;
-
- switch (status()) {
- case IcacheMissStall:
- assert(old_status == Running);
- lastIcacheStall = curTick;
- if (tickEvent.scheduled())
- tickEvent.squash();
- break;
-
- case IcacheMissComplete:
- assert(old_status == IcacheMissStall);
- if (tickEvent.squashed())
- tickEvent.reschedule(curTick + 1);
- else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + 1);
- break;
-
- case DcacheMissStall:
- assert(old_status == Running);
- lastDcacheStall = curTick;
- if (tickEvent.scheduled())
- tickEvent.squash();
- break;
-
- case Idle:
- assert(old_status == Running);
- idleFraction++;
- if (tickEvent.scheduled())
- tickEvent.squash();
- break;
-
- case Running:
- assert(old_status == Idle ||
- old_status == DcacheMissStall ||
- old_status == IcacheMissComplete);
- if (old_status == Idle && curTick != 0)
- idleFraction--;
-
- if (tickEvent.squashed())
- tickEvent.reschedule(curTick + 1);
- else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + 1);
- break;
-
- default:
- panic("can't get here");
- }
- }
+ void setStatus(Status new_status);
// statistics
virtual void regStats();
@@ -247,7 +193,8 @@ class SimpleCPU : public BaseCPU
Counter startNumLoad;
// number of idle cycles
- Statistics::Average<> idleFraction;
+ Statistics::Average<> notIdleFraction;
+ Statistics::Formula idleFraction;
// number of cycles stalled for I-cache misses
Statistics::Scalar<> icacheStallCycles;