diff options
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/memtest/memtest.cc | 22 | ||||
-rw-r--r-- | cpu/memtest/memtest.hh | 9 | ||||
-rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 2 |
3 files changed, 18 insertions, 15 deletions
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc index 051d9623a..5d608976d 100644 --- a/cpu/memtest/memtest.cc +++ b/cpu/memtest/memtest.cc @@ -40,7 +40,7 @@ #include "mem/functional_mem/main_memory.hh" #include "sim/builder.hh" #include "sim/sim_events.hh" -#include "sim/sim_stats.hh" +#include "sim/stats.hh" using namespace std; @@ -109,7 +109,6 @@ MemTest::MemTest(const string &name, // set up counters noResponseCycles = 0; numReads = 0; - numWrites = 0; tickEvent.schedule(0); } @@ -142,21 +141,23 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data) } numReads++; + numReadsStat++; - if (numReads.value() == nextProgressMessage) { - cerr << name() << ": completed " << numReads.value() - << " read accesses @ " << curTick << endl; + if (numReads == nextProgressMessage) { + ccprintf(cerr, "%s: completed %d read accesses @%d\n", + name(), numReads, curTick); nextProgressMessage += progressInterval; } - comLoadEventQueue[0]->serviceEvents(numReads.value()); + comLoadEventQueue[0]->serviceEvents(numReads); break; case Write: - numWrites++; + numWritesStat++; break; case Copy: + numCopiesStat++; break; default: @@ -187,17 +188,18 @@ MemTest::regStats() { using namespace Statistics; - numReads + + numReadsStat .name(name() + ".num_reads") .desc("number of read accesses completed") ; - numWrites + numWritesStat .name(name() + ".num_writes") .desc("number of write accesses completed") ; - numCopies + numCopiesStat .name(name() + ".num_copies") .desc("number of copy accesses completed") ; diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh index da6e180a0..f2409d54c 100644 --- a/cpu/memtest/memtest.hh +++ b/cpu/memtest/memtest.hh @@ -36,7 +36,7 @@ #include "cpu/exec_context.hh" #include "base/statistics.hh" -#include "sim/sim_stats.hh" +#include "sim/stats.hh" class MemTest : public BaseCPU { @@ -110,9 +110,10 @@ class MemTest : public BaseCPU Tick noResponseCycles; - Statistics::Scalar<> numReads; - Statistics::Scalar<> numWrites; - Statistics::Scalar<> numCopies; + uint64_t numReads; + Statistics::Scalar<> numReadsStat; + Statistics::Scalar<> numWritesStat; + Statistics::Scalar<> numCopiesStat; // called by MemCompleteEvent::process() void completeRequest(MemReqPtr &req, uint8_t *data); diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 711c81c51..f29d9d60e 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -56,7 +56,7 @@ #include "sim/host.hh" #include "sim/sim_events.hh" #include "sim/sim_object.hh" -#include "sim/sim_stats.hh" +#include "sim/stats.hh" #ifdef FULL_SYSTEM #include "base/remote_gdb.hh" |