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-rw-r--r--cpu/inst_seq.hh2
-rw-r--r--cpu/o3/cpu.cc10
-rw-r--r--cpu/ozone/cpu_builder.cc12
-rw-r--r--cpu/ozone/thread_state.hh5
4 files changed, 15 insertions, 14 deletions
diff --git a/cpu/inst_seq.hh b/cpu/inst_seq.hh
index 8de047af7..356d19df0 100644
--- a/cpu/inst_seq.hh
+++ b/cpu/inst_seq.hh
@@ -29,6 +29,8 @@
#ifndef __STD_TYPES_HH__
#define __STD_TYPES_HH__
+#include <stdint.h>
+
// inst sequence type, used to order instructions in the ready list,
// if this rolls over the ready list order temporarily will get messed
// up, but execution will continue and complete correctly
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index d322037bc..ac8c4236e 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -123,7 +123,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
physmem(system->physmem),
mem(params->mem),
#else
- pTable(params->pTable),
+// pTable(params->pTable),
#endif // FULL_SYSTEM
icacheInterface(params->icacheInterface),
@@ -238,8 +238,8 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
// Setup the page table for whichever stages need it.
#if !FULL_SYSTEM
- fetch.setPageTable(pTable);
- iew.setPageTable(pTable);
+// fetch.setPageTable(pTable);
+// iew.setPageTable(pTable);
#endif
// Setup the ROB for whichever stages need it.
@@ -885,11 +885,9 @@ template <class Impl>
void
FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
{
- unsigned tid = inst->threadNumber;
-
DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x "
"[sn:%lli]\n",
- tid, inst->readPC(), inst->seqNum);
+ inst->threadNumber, inst->readPC(), inst->seqNum);
removeInstsThisCycle = true;
diff --git a/cpu/ozone/cpu_builder.cc b/cpu/ozone/cpu_builder.cc
index 8ac6858b0..0146dd1bd 100644
--- a/cpu/ozone/cpu_builder.cc
+++ b/cpu/ozone/cpu_builder.cc
@@ -45,7 +45,7 @@ SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
#else
SimObjectVectorParam<Process *> workload;
-SimObjectParam<PageTable *> page_table;
+//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
SimObjectParam<FunctionalMemory *> mem;
@@ -159,7 +159,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
INIT_PARAM(dtb, "Data translation buffer"),
#else
INIT_PARAM(workload, "Processes to run"),
- INIT_PARAM(page_table, "Page table"),
+// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(mem, "Memory", NULL),
@@ -310,7 +310,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->dtb = dtb;
#else
params->workload = workload;
- params->pTable = page_table;
+// params->pTable = page_table;
#endif // FULL_SYSTEM
params->mem = mem;
@@ -440,7 +440,7 @@ SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
#else
SimObjectVectorParam<Process *> workload;
-SimObjectParam<PageTable *> page_table;
+//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
SimObjectParam<FunctionalMemory *> mem;
@@ -554,7 +554,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
INIT_PARAM(dtb, "Data translation buffer"),
#else
INIT_PARAM(workload, "Processes to run"),
- INIT_PARAM(page_table, "Page table"),
+// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(mem, "Memory", NULL),
@@ -705,7 +705,7 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
params->dtb = dtb;
#else
params->workload = workload;
- params->pTable = page_table;
+// params->pTable = page_table;
#endif // FULL_SYSTEM
params->mem = mem;
diff --git a/cpu/ozone/thread_state.hh b/cpu/ozone/thread_state.hh
index c6d23a63b..269fc6459 100644
--- a/cpu/ozone/thread_state.hh
+++ b/cpu/ozone/thread_state.hh
@@ -6,9 +6,10 @@
#include "arch/isa_traits.hh"
#include "cpu/exec_context.hh"
#include "cpu/thread_state.hh"
+#include "sim/process.hh"
class Event;
-class Process;
+//class Process;
#if FULL_SYSTEM
class EndQuiesceEvent;
@@ -40,7 +41,7 @@ struct OzoneThreadState : public ThreadState {
}
#else
OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
- : ThreadState(-1, _thread_num, NULL, _process, _asid),
+ : ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid),
cpu(_cpu), inSyscall(0), trapPending(0)
{
memset(&regs, 0, sizeof(TheISA::RegFile));