summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/cpu_exec_context.hh18
-rw-r--r--cpu/exec_context.hh12
-rw-r--r--cpu/simple/cpu.cc84
-rw-r--r--cpu/simple/cpu.hh14
-rw-r--r--cpu/static_inst.hh5
5 files changed, 67 insertions, 66 deletions
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 736af85ba..2c06a7b3b 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -241,17 +241,17 @@ class CPUExecContext
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{
return itb->translate(req, proxy);
}
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{
return dtb->translate(req, proxy, false);
}
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{
return dtb->translate(req, proxy, true);
}
@@ -273,17 +273,17 @@ class CPUExecContext
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
@@ -292,7 +292,7 @@ class CPUExecContext
/*
template <class T>
- Fault read(CpuRequestPtr &req, T &data)
+ Fault read(RequestPtr &req, T &data)
{
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
if (req->flags & LOCKED) {
@@ -308,7 +308,7 @@ class CPUExecContext
}
template <class T>
- Fault write(CpuRequestPtr &req, T &data)
+ Fault write(RequestPtr &req, T &data)
{
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
ExecContext *xc;
@@ -369,7 +369,7 @@ class CPUExecContext
inst = new_inst;
}
- Fault instRead(CpuRequestPtr &req)
+ Fault instRead(RequestPtr &req)
{
panic("instRead not implemented");
// return funcPhysMem->read(req, inst);
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 4e40bc48d..1f26183ab 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -152,11 +152,11 @@ class ExecContext
virtual int getInstAsid() = 0;
virtual int getDataAsid() = 0;
- virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateInstReq(RequestPtr &req) = 0;
- virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataReadReq(RequestPtr &req) = 0;
- virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
// Also somewhat obnoxious. Really only used for the TLB fault.
// However, may be quite useful in SPARC.
@@ -327,13 +327,13 @@ class ProxyExecContext : public ExecContext
int getInstAsid() { return actualXC->getInstAsid(); }
int getDataAsid() { return actualXC->getDataAsid(); }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{ return actualXC->translateInstReq(req); }
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{ return actualXC->translateDataReadReq(req); }
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{ return actualXC->translateDataWriteReq(req); }
// @todo: Do I need this?
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 88c99c566..0f1f9574a 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -155,13 +155,8 @@ SimpleCPU::CpuPort::recvRetry()
}
SimpleCPU::SimpleCPU(Params *p)
-#if !FULL_SYSTEM
: BaseCPU(p), mem(p->mem), icachePort(this),
dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
-#else
- : BaseCPU(p), icachePort(this), dcachePort(this),
- tickEvent(this, p->width), cpuXC(NULL)
-#endif
{
_status = Idle;
@@ -175,24 +170,24 @@ SimpleCPU::SimpleCPU(Params *p)
xcProxy = cpuXC->getProxy();
#if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
- ifetch_req = new CpuRequest;
- ifetch_req->asid = 0;
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req = new Request(true);
+ ifetch_req->setAsid(0);
+ ifetch_req->setSize(sizeof(MachInst));
ifetch_pkt = new Packet;
ifetch_pkt->cmd = Read;
ifetch_pkt->data = (uint8_t *)&inst;
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
- data_read_req = new CpuRequest;
- data_read_req->asid = 0;
+ data_read_req = new Request(true);
+ data_read_req->setAsid(0);
data_read_pkt = new Packet;
data_read_pkt->cmd = Read;
data_read_pkt->data = new uint8_t[8];
data_read_pkt->req = data_read_req;
- data_write_req = new CpuRequest;
- data_write_req->asid = 0;
+ data_write_req = new Request(true);
+ data_write_req->setAsid(0);
data_write_pkt = new Packet;
data_write_pkt->cmd = Write;
data_write_pkt->req = data_write_req;
@@ -483,7 +478,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
}
if (traceData) {
- traceData->setAddr(addr);
+ traceData->setAddr(data_read_req->getVaddr());
}
// @todo: Figure out a way to create a Fault from the packet result.
@@ -493,13 +488,13 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
// memReq->reset(addr, sizeof(T), flags);
#if SIMPLE_CPU_MEM_TIMING
- CpuRequest *data_read_req = new CpuRequest;
+ CpuRequest *data_read_req = new Request(true);
#endif
- data_read_req->vaddr = addr;
- data_read_req->size = sizeof(T);
- data_read_req->flags = flags;
- data_read_req->time = curTick;
+ data_read_req->setVaddr(addr);
+ data_read_req->setSize(sizeof(T));
+ data_read_req->setFlags(flags);
+ data_read_req->setTime(curTick);
// translate to physical address
Fault fault = cpuXC->translateDataReadReq(data_read_req);
@@ -512,7 +507,8 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
data_read_pkt->req = data_read_req;
data_read_pkt->data = new uint8_t[8];
#endif
- data_read_pkt->addr = data_read_req->paddr;
+ data_read_pkt->reset();
+ data_read_pkt->addr = data_read_req->getPaddr();
data_read_pkt->size = sizeof(T);
sendDcacheRequest(data_read_pkt);
@@ -559,7 +555,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
}
*/
// This will need a new way to tell if it has a dcache attached.
- if (data_read_req->flags & UNCACHEABLE)
+ if (data_read_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Read");
return fault;
@@ -612,10 +608,10 @@ template <class T>
Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- data_write_req->vaddr = addr;
- data_write_req->time = curTick;
- data_write_req->size = sizeof(T);
- data_write_req->flags = flags;
+ data_write_req->setVaddr(addr);
+ data_write_req->setTime(curTick);
+ data_write_req->setSize(sizeof(T));
+ data_write_req->setFlags(flags);
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
@@ -628,9 +624,10 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
data_write_pkt->data = new uint8_t[64];
memcpy(data_write_pkt->data, &data, sizeof(T));
#else
+ data_write_pkt->reset();
data_write_pkt->data = (uint8_t *)&data;
#endif
- data_write_pkt->addr = data_write_req->paddr;
+ data_write_pkt->addr = data_write_req->getPaddr();
data_write_pkt->size = sizeof(T);
sendDcacheRequest(data_write_pkt);
@@ -664,9 +661,14 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
*res = data_write_pkt->result;
// This will need a new way to tell if it's hooked up to a cache or not.
- if (data_write_req->flags & UNCACHEABLE)
+ if (data_write_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Write");
+ // @todo this is a hack and only works on uniprocessor systems some one else
+ // can implement LL/SC.
+ if (data_write_req->getFlags() & LOCKED)
+ *res = 1;
+
// If the write needs to have a fault on the access, consider calling
// changeStatus() and changing it to "bad addr write" or something.
return fault;
@@ -962,26 +964,23 @@ SimpleCPU::tick()
// Try to fetch an instruction
// set up memory request for instruction fetch
-#if FULL_SYSTEM
-#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
-#else
-#define IFETCH_FLAGS(pc) 0
-#endif
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
cpuXC->readNextPC(),cpuXC->readNextNPC());
#if SIMPLE_CPU_MEM_TIMING
CpuRequest *ifetch_req = new CpuRequest();
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req->setSize(sizeof(MachInst));
#endif
- ifetch_req->vaddr = cpuXC->readPC() & ~3;
- ifetch_req->time = curTick;
-
-/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
- IFETCH_FLAGS(xc->regs.pc));
-*/
+ ifetch_req->resetMin();
+ ifetch_req->setVaddr(cpuXC->readPC() & ~3);
+ ifetch_req->setTime(curTick);
+#if FULL_SYSTEM
+ ifetch_req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
+#else
+ ifetch_req->setFlags(0);
+#endif
fault = cpuXC->translateInstReq(ifetch_req);
@@ -993,7 +992,8 @@ SimpleCPU::tick()
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
#endif
- ifetch_pkt->addr = ifetch_req->paddr;
+ ifetch_pkt->reset();
+ ifetch_pkt->addr = ifetch_req->getPaddr();
sendIcacheRequest(ifetch_pkt);
#if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC
@@ -1133,6 +1133,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
+ SimObjectParam<MemObject *> mem;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
@@ -1141,7 +1142,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
Param<int> cpu_id;
Param<Tick> profile;
#else
- SimObjectParam<MemObject *> mem;
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
@@ -1164,6 +1164,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
+ INIT_PARAM(mem, "memory"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
@@ -1172,7 +1173,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
- INIT_PARAM(mem, "memory"),
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
@@ -1199,6 +1199,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->width = width;
+ params->mem = mem;
#if FULL_SYSTEM
params->itb = itb;
@@ -1207,7 +1208,6 @@ CREATE_SIM_OBJECT(SimpleCPU)
params->cpu_id = cpu_id;
params->profile = profile;
#else
- params->mem = mem;
params->process = workload;
#endif
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 9da7072bf..c3ff5cf3d 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -178,11 +178,11 @@ class SimpleCPU : public BaseCPU
struct Params : public BaseCPU::Params
{
int width;
+ MemObject *mem;
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
#else
- MemObject *mem;
Process *process;
#endif
};
@@ -210,12 +210,12 @@ class SimpleCPU : public BaseCPU
#if SIMPLE_CPU_MEM_TIMING
Packet *retry_pkt;
#elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
- CpuRequest *ifetch_req;
- Packet *ifetch_pkt;
- CpuRequest *data_read_req;
- Packet *data_read_pkt;
- CpuRequest *data_write_req;
- Packet *data_write_pkt;
+ Request *ifetch_req;
+ Packet *ifetch_pkt;
+ Request *data_read_req;
+ Packet *data_read_pkt;
+ Request *data_write_req;
+ Packet *data_write_pkt;
#endif
// Pointer to the sampler that is telling us to switchover.
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index a200e2849..f0b75c10e 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -397,8 +397,9 @@ class StaticInst : public StaticInstBase
int getRs() { return (machInst & 0x03E00000) >> 21; } //25...21
int getRt() { return (machInst & 0x001F0000) >> 16; } //20...16
int getRd() { return (machInst & 0x0000F800) >> 11; } //15...11
- int getOpname(){ return (machInst & 0x0000003F); }//5...0
- int getBranch(){ return (machInst & 0x0000FFFF); }//5...0
+ int getImm() { return (machInst & 0x0000FFFF); } //15...0
+ int getFunction(){ return (machInst & 0x0000003F); }//5...0
+ int getBranch(){ return (machInst & 0x0000FFFF); }//15...0
int getJump(){ return (machInst & 0x03FFFFFF); }//5...0
int getHint(){ return (machInst & 0x000007C0) >> 6; } //10...6
std::string getName() { return mnemonic; }
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-11 22:08:28 +0000