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-rw-r--r--cpu/cpu_exec_context.cc21
-rw-r--r--cpu/cpu_exec_context.hh17
-rw-r--r--cpu/exec_context.hh14
-rw-r--r--cpu/exetrace.cc5
-rw-r--r--cpu/simple/cpu.cc17
5 files changed, 39 insertions, 35 deletions
diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index 0a3dc5675..a3e6cc432 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -42,10 +42,10 @@
#include "kern/kernel_stats.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
-#include "sim/system.hh"
#include "arch/stacktrace.hh"
#else
#include "sim/process.hh"
+#include "sim/system.hh"
#include "mem/translating_port.hh"
#endif
@@ -54,12 +54,11 @@ using namespace std;
// constructor
#if FULL_SYSTEM
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
- AlphaITB *_itb, AlphaDTB *_dtb,
- Memory *_mem)
+ AlphaITB *_itb, AlphaDTB *_dtb)
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
- cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
- dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
- profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0)
+ cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
+ dtb(_dtb), memctrl(_sys->memctrl), profile(NULL),
+ quiesceEvent(this), func_exe_inst(0), storeCondFailures(0)
{
proxy = new ProxyExecContext<CPUExecContext>(this);
@@ -81,13 +80,19 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
}
#else
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
- Process *_process, int _asid, Port *mem_port)
+ Process *_process, int _asid, MemObject* memobj)
: _status(ExecContext::Unallocated),
cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
lastSuspend(0), process(_process), asid(_asid),
func_exe_inst(0), storeCondFailures(0)
{
- port = new TranslatingPort(mem_port, process->pTable);
+ /* Use this port to for syscall emulation writes to memory. */
+ Port *mem_port;
+ port = new TranslatingPort(process->pTable, false);
+ mem_port = memobj->getPort("functional");
+ mem_port->setPeer(port);
+ port->setPeer(mem_port);
+
memset(&regs, 0, sizeof(RegFile));
proxy = new ProxyExecContext<CPUExecContext>(this);
}
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 236619752..7ceb7f2d8 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -121,9 +121,6 @@ class CPUExecContext
System *system;
- /// Port that syscalls can use to access memory (provides translation step).
- TranslatingPort *port;
-// Memory *mem;
#if FULL_SYSTEM
AlphaITB *itb;
@@ -167,6 +164,9 @@ class CPUExecContext
void profileSample();
#else
+ /// Port that syscalls can use to access memory (provides translation step).
+ TranslatingPort *port;
+
Process *process;
// Address space ID. Note that this is used for TIMING cache
@@ -203,9 +203,10 @@ class CPUExecContext
// constructor: initialize context from given process structure
#if FULL_SYSTEM
CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
- AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
+ AlphaITB *_itb, AlphaDTB *_dtb);
#else
- CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, Port *mem_port);
+ CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
+ MemObject *memobj);
// Constructor to use XC to pass reg file around. Not used for anything
// else.
CPUExecContext(RegFile *regFile);
@@ -219,8 +220,6 @@ class CPUExecContext
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
- TranslatingPort *getMemPort() { return port; }
-
BaseCPU *getCpuPtr() { return cpu; }
ExecContext *getProxy() { return proxy; }
@@ -230,8 +229,6 @@ class CPUExecContext
#if FULL_SYSTEM
System *getSystemPtr() { return system; }
- PhysicalMemory *getPhysMemPtr() { return physmem; }
-
AlphaITB *getITBPtr() { return itb; }
AlphaDTB *getDTBPtr() { return dtb; }
@@ -255,6 +252,8 @@ class CPUExecContext
}
#else
+ TranslatingPort *getMemPort() { return port; }
+
Process *getProcessPtr() { return process; }
int getInstAsid() { return asid; }
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 2fdb19c73..8f93875a1 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -36,14 +36,12 @@
#include "sim/serialize.hh"
#include "sim/byteswap.hh"
-// forward declaration: see functional_memory.hh
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
class AlphaDTB;
class AlphaITB;
class BaseCPU;
class Event;
-class PhysicalMemory;
class TranslatingPort;
class Process;
class System;
@@ -83,8 +81,6 @@ class ExecContext
virtual ~ExecContext() { };
- virtual TranslatingPort *getMemPort() = 0;
-
virtual BaseCPU *getCpuPtr() = 0;
virtual void setCpuId(int id) = 0;
@@ -94,12 +90,12 @@ class ExecContext
#if FULL_SYSTEM
virtual System *getSystemPtr() = 0;
- virtual PhysicalMemory *getPhysMemPtr() = 0;
-
virtual AlphaITB *getITBPtr() = 0;
virtual AlphaDTB * getDTBPtr() = 0;
#else
+ virtual TranslatingPort *getMemPort() = 0;
+
virtual Process *getProcessPtr() = 0;
#endif
@@ -251,8 +247,6 @@ class ProxyExecContext : public ExecContext
public:
- TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
-
BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
void setCpuId(int id) { actualXC->setCpuId(id); }
@@ -262,12 +256,12 @@ class ProxyExecContext : public ExecContext
#if FULL_SYSTEM
System *getSystemPtr() { return actualXC->getSystemPtr(); }
- PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
-
AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
#else
+ TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
+
Process *getProcessPtr() { return actualXC->getProcessPtr(); }
#endif
diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc
index ebb719b2c..4db72320c 100644
--- a/cpu/exetrace.cc
+++ b/cpu/exetrace.cc
@@ -29,11 +29,12 @@
#include <fstream>
#include <iomanip>
-#include "sim/param.hh"
-#include "cpu/exetrace.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
+#include "sim/param.hh"
+#include "sim/system.hh"
using namespace std;
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 4aaf81fa0..88c99c566 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -64,8 +64,8 @@
#if FULL_SYSTEM
#include "base/remote_gdb.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
+//#include "mem/functional/memory_control.hh"
+//#include "mem/functional/physical.hh"
#include "sim/system.hh"
#include "arch/tlb.hh"
#include "arch/stacktrace.hh"
@@ -155,16 +155,21 @@ SimpleCPU::CpuPort::recvRetry()
}
SimpleCPU::SimpleCPU(Params *p)
+#if !FULL_SYSTEM
: BaseCPU(p), mem(p->mem), icachePort(this),
dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
+#else
+ : BaseCPU(p), icachePort(this), dcachePort(this),
+ tickEvent(this, p->width), cpuXC(NULL)
+#endif
{
_status = Idle;
#if FULL_SYSTEM
- cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
+ cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
#else
- cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0,
- &dcachePort);
+ cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
+ /* asid */ 0, mem);
#endif // !FULL_SYSTEM
xcProxy = cpuXC->getProxy();
@@ -899,7 +904,7 @@ SimpleCPU::tick()
#if FULL_SYSTEM
if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
- status() != IcacheMissComplete) {
+ status() != IcacheAccessComplete) {
int ipl = 0;
int summary = 0;
checkInterrupts = false;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 15:52:20 +0000