4 files changed, 40 insertions, 24 deletions

diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 037319a8f..edab25d0b 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -51,7 +51,7 @@ using namespace std;
 #if FULL_SYSTEM
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
                          AlphaITB *_itb, AlphaDTB *_dtb,
-                         FunctionalMemory *_mem)
+                         Memory *_mem)
     : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
       cpu_id(-1), mem(_mem), itb(_itb), dtb(_dtb), system(_sys),
       memctrl(_sys->memctrl), physmem(_sys->physmem),
@@ -77,7 +77,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
 }
 #else
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
-                         FunctionalMemory *_mem, Process *_process, int _asid)
+                         Memory *_mem, Process *_process, int _asid)
     : _status(ExecContext::Unallocated),
       cpu(_cpu), thread_num(_thread_num), cpu_id(-1),
       system(_system), mem(_mem),
diff --git a/cpu/pc_event.hh b/cpu/pc_event.hh
index 7fa3902cc..585aba0f1 100644
--- a/cpu/pc_event.hh
+++ b/cpu/pc_event.hh
@@ -31,17 +31,12 @@
 
 #include <vector>
 
-#include "mem/mem_req.hh"
-
 class ExecContext;
 class PCEventQueue;
 
 class PCEvent
 {
   protected:
-    static const Addr badpc = MemReq::inval_addr;
-
-  protected:
     std::string description;
     PCEventQueue *queue;
     Addr evpc;
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 0760f978c..b6823fb63 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -102,17 +102,42 @@ SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
 {
 }
 
-void SimpleCPU::CacheCompletionEvent::process()
+
+bool
+SimpleCPU::CpuPort::recvTiming(Packet &pkt)
 {
-    cpu->processCacheCompletion();
+    cpu->processResponse(pkt);
+    return true;
 }
 
-const char *
-SimpleCPU::CacheCompletionEvent::description()
+Tick
+SimpleCPU::CpuPort::recvAtomic(Packet &pkt)
 {
-    return "SimpleCPU cache completion event";
+    panic("CPU doesn't expect callback!");
+    return curTick;
 }
 
+void
+SimpleCPU::CpuPort::recvFunctional(Packet &pkt)
+{
+    panic("CPU doesn't expect callback!");
+}
+
+void
+SimpleCPU::CpuPort::recvStatusChange(Status status)
+{
+    cpu->recvStatusChange(status);
+}
+
+Packet *
+SimpleCPU::CpuPort::recvRetry()
+{
+    return cpu->processRetry();
+}
+
+
+
+
 SimpleCPU::SimpleCPU(Params *p)
     : BaseCPU(p), tickEvent(this, p->width), xc(NULL),
       cacheCompletionEvent(this), dcachePort(this), icachePort(this)
@@ -697,9 +722,9 @@ SimpleCPU::sendDcacheRequest()
 void
 SimpleCPU::processResponse(Packet *response)
 {
-    // For what things is the CPU the consumer of the packet it sent out?
-    // This may create a memory leak if that's the case and it's expected of the
-    // SimpleCPU to delete its own packet.
+    // For what things is the CPU the consumer of the packet it sent
+    // out?  This may create a memory leak if that's the case and it's
+    // expected of the SimpleCPU to delete its own packet.
     pkt = response;
 
     switch (status()) {
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 42fec55f1..3d445b001 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -79,19 +79,15 @@ class SimpleCPU : public BaseCPU
 
       protected:
 
-        virtual bool recvTiming(Packet &pkt)
-        { cpu->processCacheCompletion(pkt); return true; }
+        virtual bool recvTiming(Packet &pkt);
 
-        virtual Tick recvAtomic(Packet &pkt)
-        { panic("CPU doesn't expect callback!"); return curTick; }
+        virtual Tick recvAtomic(Packet &pkt);
 
-        virtual void recvFunctional(Packet &pkt)
-        { panic("CPU doesn't expect callback!"); }
+        virtual void recvFunctional(Packet &pkt);
 
-        virtual void recvStatusChange(Status status)
-        { cpu->recvStatusChange(status); }
+        virtual void recvStatusChange(Status status);
 
-        virtual Packet *recvRetry() { return cpu->processRetry(); }
+        virtual Packet *recvRetry();
     };
 
     CpuPort icachePort;