diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/o3/2bit_local_pred.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/alpha_cpu.hh | 8 | ||||
| -rw-r--r-- | cpu/o3/alpha_cpu_impl.hh | 29 | ||||
| -rw-r--r-- | cpu/o3/alpha_dyn_inst.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/alpha_impl.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/alpha_params.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/btb.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/comm.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/commit.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/cpu.cc | 82 | ||||
| -rw-r--r-- | cpu/o3/cpu.hh | 14 | ||||
| -rw-r--r-- | cpu/o3/cpu_policy.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/decode.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/fetch.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/free_list.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/iew.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/inst_queue.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/mem_dep_unit.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/ras.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/regfile.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/rename.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/rename_map.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/rob.cc | 27 | ||||
| -rw-r--r-- | cpu/o3/rob.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/rob_impl.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/sat_counter.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/store_set.hh | 6 | ||||
| -rw-r--r-- | cpu/o3/tournament_pred.hh | 6 |
28 files changed, 176 insertions, 122 deletions
diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh index 856407f56..a97ce455c 100644 --- a/cpu/o3/2bit_local_pred.hh +++ b/cpu/o3/2bit_local_pred.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__ -#define __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__ +#ifndef __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__ +#define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__ // For Addr type. #include "arch/alpha/isa_traits.hh" @@ -83,4 +83,4 @@ class DefaultBP unsigned indexMask; }; -#endif // __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__ +#endif // __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__ diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 386c60b0c..3c679c3b2 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -29,13 +29,13 @@ // Todo: Find all the stuff in ExecContext and ev5 that needs to be // specifically designed for this CPU. -#ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__ -#define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__ +#ifndef __CPU_O3_CPU_ALPHA_FULL_CPU_HH__ +#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__ #include "cpu/o3/cpu.hh" template <class Impl> -class AlphaFullCPU : public FullBetaCPU<Impl> +class AlphaFullCPU : public FullO3CPU<Impl> { public: typedef typename Impl::ISA AlphaISA; @@ -288,4 +288,4 @@ class AlphaFullCPU : public FullBetaCPU<Impl> }; -#endif // __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__ +#endif // __CPU_O3_CPU_ALPHA_FULL_CPU_HH__ diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 822d58f1f..146186e2f 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -1,3 +1,30 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include "base/cprintf.hh" #include "base/statistics.hh" @@ -22,7 +49,7 @@ template <class Impl> AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms) - : FullBetaCPU<Impl>(params) + : FullO3CPU<Impl>(params) { DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n"); diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index 0b6b62f35..8a9a681d2 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_ALPHA_DYN_INST_HH__ -#define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__ +#ifndef __CPU_O3_CPU_ALPHA_DYN_INST_HH__ +#define __CPU_O3_CPU_ALPHA_DYN_INST_HH__ #include "cpu/base_dyn_inst.hh" #include "cpu/o3/alpha_cpu.hh" @@ -231,5 +231,5 @@ class AlphaDynInst : public BaseDynInst<Impl> } }; -#endif // __CPU_BETA_CPU_ALPHA_DYN_INST_HH__ +#endif // __CPU_O3_CPU_ALPHA_DYN_INST_HH__ diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh index eb3c07dd3..6c1156041 100644 --- a/cpu/o3/alpha_impl.hh +++ b/cpu/o3/alpha_impl.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_ALPHA_IMPL_HH__ -#define __CPU_BETA_CPU_ALPHA_IMPL_HH__ +#ifndef __CPU_O3_CPU_ALPHA_IMPL_HH__ +#define __CPU_O3_CPU_ALPHA_IMPL_HH__ #include "arch/alpha/isa_traits.hh" @@ -79,4 +79,4 @@ struct AlphaSimpleImpl }; }; -#endif // __CPU_BETA_CPU_ALPHA_IMPL_HH__ +#endif // __CPU_O3_CPU_ALPHA_IMPL_HH__ diff --git a/cpu/o3/alpha_params.hh b/cpu/o3/alpha_params.hh index 5c8f61f3b..77e6f3649 100644 --- a/cpu/o3/alpha_params.hh +++ b/cpu/o3/alpha_params.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__ -#define __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__ +#ifndef __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__ +#define __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__ #include "cpu/o3/cpu.hh" @@ -160,4 +160,4 @@ class AlphaSimpleParams : public BaseFullCPU::Params bool defReg; }; -#endif // __CPU_BETA_CPU_ALPHA_PARAMS_HH__ +#endif // __CPU_O3_CPU_ALPHA_PARAMS_HH__ diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh index 66ae931e4..a4ddfecb4 100644 --- a/cpu/o3/btb.hh +++ b/cpu/o3/btb.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_BTB_HH__ -#define __CPU_BETA_CPU_BTB_HH__ +#ifndef __CPU_O3_CPU_BTB_HH__ +#define __CPU_O3_CPU_BTB_HH__ // For Addr type. #include "arch/alpha/isa_traits.hh" @@ -77,4 +77,4 @@ class DefaultBTB unsigned tagShiftAmt; }; -#endif // __CPU_BETA_CPU_BTB_HH__ +#endif // __CPU_O3_CPU_BTB_HH__ diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index 475ab8df8..e4de1d304 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_COMM_HH__ -#define __CPU_BETA_CPU_COMM_HH__ +#ifndef __CPU_O3_CPU_COMM_HH__ +#define __CPU_O3_CPU_COMM_HH__ #include <vector> @@ -160,4 +160,4 @@ struct TimeBufStruct { commitComm commitInfo; }; -#endif //__CPU_BETA_CPU_COMM_HH__ +#endif //__CPU_O3_CPU_COMM_HH__ diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh index 60afe1fd4..6ddc8d6b9 100644 --- a/cpu/o3/commit.hh +++ b/cpu/o3/commit.hh @@ -40,8 +40,8 @@ // Probably not a big deal if the IPR stuff isn't cycle accurate. Can just // have the original function handle writing to the IPR register. -#ifndef __CPU_BETA_CPU_SIMPLE_COMMIT_HH__ -#define __CPU_BETA_CPU_SIMPLE_COMMIT_HH__ +#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__ +#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__ #include "base/statistics.hh" #include "base/timebuf.hh" @@ -178,4 +178,4 @@ class SimpleCommit Stats::Distribution<> n_committed_dist; }; -#endif // __CPU_BETA_CPU_SIMPLE_COMMIT_HH__ +#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__ diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index a91c36679..b447439c0 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -46,28 +46,28 @@ BaseFullCPU::BaseFullCPU(Params ¶ms) } template <class Impl> -FullBetaCPU<Impl>::TickEvent::TickEvent(FullBetaCPU<Impl> *c) +FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) { } template <class Impl> void -FullBetaCPU<Impl>::TickEvent::process() +FullO3CPU<Impl>::TickEvent::process() { cpu->tick(); } template <class Impl> const char * -FullBetaCPU<Impl>::TickEvent::description() +FullO3CPU<Impl>::TickEvent::description() { - return "FullBetaCPU tick event"; + return "FullO3CPU tick event"; } //Call constructor to all the pipeline stages here template <class Impl> -FullBetaCPU<Impl>::FullBetaCPU(Params ¶ms) +FullO3CPU<Impl>::FullO3CPU(Params ¶ms) #ifdef FULL_SYSTEM : BaseFullCPU(params), #else @@ -161,7 +161,7 @@ FullBetaCPU<Impl>::FullBetaCPU(Params ¶ms) // The stages also need their CPU pointer setup. However this must be // done at the upper level CPU because they have pointers to the upper - // level CPU, and not this FullBetaCPU. + // level CPU, and not this FullO3CPU. // Give each of the stages the time buffer they will use. fetch.setTimeBuffer(&timeBuffer); @@ -194,22 +194,22 @@ FullBetaCPU<Impl>::FullBetaCPU(Params ¶ms) } template <class Impl> -FullBetaCPU<Impl>::~FullBetaCPU() +FullO3CPU<Impl>::~FullO3CPU() { } template <class Impl> void -FullBetaCPU<Impl>::fullCPURegStats() +FullO3CPU<Impl>::fullCPURegStats() { // Register any of the FullCPU's stats here. } template <class Impl> void -FullBetaCPU<Impl>::tick() +FullO3CPU<Impl>::tick() { - DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullBetaCPU.\n"); + DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); //Tick each of the stages if they're actually running. //Will want to figure out a way to unschedule itself if they're all @@ -238,7 +238,7 @@ FullBetaCPU<Impl>::tick() template <class Impl> void -FullBetaCPU<Impl>::init() +FullO3CPU<Impl>::init() { if(!deferRegistration) { @@ -278,7 +278,7 @@ FullBetaCPU<Impl>::init() template <class Impl> void -FullBetaCPU<Impl>::activateContext(int thread_num, int delay) +FullO3CPU<Impl>::activateContext(int thread_num, int delay) { // Needs to set each stage to running as well. @@ -289,35 +289,35 @@ FullBetaCPU<Impl>::activateContext(int thread_num, int delay) template <class Impl> void -FullBetaCPU<Impl>::suspendContext(int thread_num) +FullO3CPU<Impl>::suspendContext(int thread_num) { panic("suspendContext unimplemented!"); } template <class Impl> void -FullBetaCPU<Impl>::deallocateContext(int thread_num) +FullO3CPU<Impl>::deallocateContext(int thread_num) { panic("deallocateContext unimplemented!"); } template <class Impl> void -FullBetaCPU<Impl>::haltContext(int thread_num) +FullO3CPU<Impl>::haltContext(int thread_num) { panic("haltContext unimplemented!"); } template <class Impl> void -FullBetaCPU<Impl>::switchOut() +FullO3CPU<Impl>::switchOut() { - panic("FullBetaCPU does not have a switch out function.\n"); + panic("FullO3CPU does not have a switch out function.\n"); } template <class Impl> void -FullBetaCPU<Impl>::takeOverFrom(BaseCPU *oldCPU) +FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) { BaseCPU::takeOverFrom(oldCPU); @@ -336,7 +336,7 @@ FullBetaCPU<Impl>::takeOverFrom(BaseCPU *oldCPU) template <class Impl> InstSeqNum -FullBetaCPU<Impl>::getAndIncrementInstSeq() +FullO3CPU<Impl>::getAndIncrementInstSeq() { // Hopefully this works right. return globalSeqNum++; @@ -344,91 +344,91 @@ FullBetaCPU<Impl>::getAndIncrementInstSeq() template <class Impl> uint64_t -FullBetaCPU<Impl>::readIntReg(int reg_idx) +FullO3CPU<Impl>::readIntReg(int reg_idx) { return regFile.readIntReg(reg_idx); } template <class Impl> float -FullBetaCPU<Impl>::readFloatRegSingle(int reg_idx) +FullO3CPU<Impl>::readFloatRegSingle(int reg_idx) { return regFile.readFloatRegSingle(reg_idx); } template <class Impl> double -FullBetaCPU<Impl>::readFloatRegDouble(int reg_idx) +FullO3CPU<Impl>::readFloatRegDouble(int reg_idx) { return regFile.readFloatRegDouble(reg_idx); } template <class Impl> uint64_t -FullBetaCPU<Impl>::readFloatRegInt(int reg_idx) +FullO3CPU<Impl>::readFloatRegInt(int reg_idx) { return regFile.readFloatRegInt(reg_idx); } template <class Impl> void -FullBetaCPU<Impl>::setIntReg(int reg_idx, uint64_t val) +FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) { regFile.setIntReg(reg_idx, val); } template <class Impl> void -FullBetaCPU<Impl>::setFloatRegSingle(int reg_idx, float val) +FullO3CPU<Impl>::setFloatRegSingle(int reg_idx, float val) { regFile.setFloatRegSingle(reg_idx, val); } template <class Impl> void -FullBetaCPU<Impl>::setFloatRegDouble(int reg_idx, double val) +FullO3CPU<Impl>::setFloatRegDouble(int reg_idx, double val) { regFile.setFloatRegDouble(reg_idx, val); } template <class Impl> void -FullBetaCPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val) +FullO3CPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val) { regFile.setFloatRegInt(reg_idx, val); } template <class Impl> uint64_t -FullBetaCPU<Impl>::readPC() +FullO3CPU<Impl>::readPC() { return regFile.readPC(); } template <class Impl> void -FullBetaCPU<Impl>::setNextPC(uint64_t val) +FullO3CPU<Impl>::setNextPC(uint64_t val) { regFile.setNextPC(val); } template <class Impl> void -FullBetaCPU<Impl>::setPC(Addr new_PC) +FullO3CPU<Impl>::setPC(Addr new_PC) { regFile.setPC(new_PC); } template <class Impl> void -FullBetaCPU<Impl>::addInst(DynInstPtr &inst) +FullO3CPU<Impl>::addInst(DynInstPtr &inst) { instList.push_back(inst); } template <class Impl> void -FullBetaCPU<Impl>::instDone() +FullO3CPU<Impl>::instDone() { // Keep an instruction count. numInsts++; @@ -439,7 +439,7 @@ FullBetaCPU<Impl>::instDone() template <class Impl> void -FullBetaCPU<Impl>::removeBackInst(DynInstPtr &inst) +FullO3CPU<Impl>::removeBackInst(DynInstPtr &inst) { DynInstPtr inst_to_delete; @@ -465,7 +465,7 @@ FullBetaCPU<Impl>::removeBackInst(DynInstPtr &inst) template <class Impl> void -FullBetaCPU<Impl>::removeFrontInst(DynInstPtr &inst) +FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) { DynInstPtr inst_to_remove; @@ -482,7 +482,7 @@ FullBetaCPU<Impl>::removeFrontInst(DynInstPtr &inst) template <class Impl> void -FullBetaCPU<Impl>::removeInstsNotInROB() +FullO3CPU<Impl>::removeInstsNotInROB() { DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " "list.\n"); @@ -494,7 +494,7 @@ FullBetaCPU<Impl>::removeInstsNotInROB() template <class Impl> void -FullBetaCPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num) +FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num) { DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " "list.\n"); @@ -522,14 +522,14 @@ FullBetaCPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num) template <class Impl> void -FullBetaCPU<Impl>::removeAllInsts() +FullO3CPU<Impl>::removeAllInsts() { instList.clear(); } template <class Impl> void -FullBetaCPU<Impl>::dumpInsts() +FullO3CPU<Impl>::dumpInsts() { int num = 0; typename list<DynInstPtr>::iterator inst_list_it = instList.begin(); @@ -546,10 +546,10 @@ FullBetaCPU<Impl>::dumpInsts() template <class Impl> void -FullBetaCPU<Impl>::wakeDependents(DynInstPtr &inst) +FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) { iew.wakeDependents(inst); } -// Forward declaration of FullBetaCPU. -template class FullBetaCPU<AlphaSimpleImpl>; +// Forward declaration of FullO3CPU. +template class FullO3CPU<AlphaSimpleImpl>; diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index df86308a8..10f60b5da 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -33,8 +33,8 @@ //itself properly. Threads! // Avoid running stages and advancing queues if idle/stalled. -#ifndef __CPU_BETA_CPU_FULL_CPU_HH__ -#define __CPU_BETA_CPU_FULL_CPU_HH__ +#ifndef __CPU_O3_CPU_FULL_CPU_HH__ +#define __CPU_O3_CPU_FULL_CPU_HH__ #include <iostream> #include <list> @@ -73,7 +73,7 @@ class BaseFullCPU : public BaseCPU }; template <class Impl> -class FullBetaCPU : public BaseFullCPU +class FullO3CPU : public BaseFullCPU { public: //Put typedefs from the Impl here. @@ -96,10 +96,10 @@ class FullBetaCPU : public BaseFullCPU class TickEvent : public Event { private: - FullBetaCPU<Impl> *cpu; + FullO3CPU<Impl> *cpu; public: - TickEvent(FullBetaCPU<Impl> *c); + TickEvent(FullO3CPU<Impl> *c); void process(); const char *description(); }; @@ -123,8 +123,8 @@ class FullBetaCPU : public BaseFullCPU } public: - FullBetaCPU(Params ¶ms); - ~FullBetaCPU(); + FullO3CPU(Params ¶ms); + ~FullO3CPU(); void fullCPURegStats(); diff --git a/cpu/o3/cpu_policy.hh b/cpu/o3/cpu_policy.hh index 2b53b436d..41f06f81b 100644 --- a/cpu/o3/cpu_policy.hh +++ b/cpu/o3/cpu_policy.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_CPU_POLICY_HH__ -#define __CPU_BETA_CPU_CPU_POLICY_HH__ +#ifndef __CPU_O3_CPU_CPU_POLICY_HH__ +#define __CPU_O3_CPU_CPU_POLICY_HH__ #include "cpu/o3/bpred_unit.hh" #include "cpu/o3/free_list.hh" @@ -85,4 +85,4 @@ struct SimpleCPUPolicy }; -#endif //__CPU_BETA_CPU_CPU_POLICY_HH__ +#endif //__CPU_O3_CPU_CPU_POLICY_HH__ diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh index 7b89bf288..42313d83a 100644 --- a/cpu/o3/decode.hh +++ b/cpu/o3/decode.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__ -#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__ +#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__ +#define __CPU_O3_CPU_SIMPLE_DECODE_HH__ #include <queue> @@ -166,4 +166,4 @@ class SimpleDecode Stats::Scalar<> decodeSquashedInsts; }; -#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__ +#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__ diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index ad0453ed5..a63010762 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -29,8 +29,8 @@ // Todo: SMT fetch, // Add a way to get a stage's current status. -#ifndef __CPU_BETA_CPU_SIMPLE_FETCH_HH__ -#define __CPU_BETA_CPU_SIMPLE_FETCH_HH__ +#ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__ +#define __CPU_O3_CPU_SIMPLE_FETCH_HH__ #include "base/statistics.hh" #include "base/timebuf.hh" @@ -221,4 +221,4 @@ class SimpleFetch Stats::Distribution<> fetch_nisn_dist; }; -#endif //__CPU_BETA_CPU_SIMPLE_FETCH_HH__ +#endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__ diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh index 09d7557a3..733d142fc 100644 --- a/cpu/o3/free_list.hh +++ b/cpu/o3/free_list.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_FREE_LIST_HH__ -#define __CPU_BETA_CPU_FREE_LIST_HH__ +#ifndef __CPU_O3_CPU_FREE_LIST_HH__ +#define __CPU_O3_CPU_FREE_LIST_HH__ #include <iostream> #include <queue> @@ -192,4 +192,4 @@ SimpleFreeList::addFloatReg(PhysRegIndex freed_reg) freeFloatRegs.push(freed_reg); } -#endif // __CPU_BETA_CPU_FREE_LIST_HH__ +#endif // __CPU_O3_CPU_FREE_LIST_HH__ diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh index 10979801c..69cd3799a 100644 --- a/cpu/o3/iew.hh +++ b/cpu/o3/iew.hh @@ -30,8 +30,8 @@ //Need to handle delaying writes to the writeback bus if it's full at the //given time. -#ifndef __CPU_BETA_CPU_SIMPLE_IEW_HH__ -#define __CPU_BETA_CPU_SIMPLE_IEW_HH__ +#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__ +#define __CPU_O3_CPU_SIMPLE_IEW_HH__ #include <queue> @@ -236,4 +236,4 @@ class SimpleIEW Stats::Scalar<> predictedTakenIncorrect; }; -#endif // __CPU_BETA_CPU_IEW_HH__ +#endif // __CPU_O3_CPU_IEW_HH__ diff --git a/cpu/o3/inst_queue.hh b/cpu/o3/inst_queue.hh index 02dc1222d..43fe96c49 100644 --- a/cpu/o3/inst_queue.hh +++ b/cpu/o3/inst_queue.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_INST_QUEUE_HH__ -#define __CPU_BETA_CPU_INST_QUEUE_HH__ +#ifndef __CPU_O3_CPU_INST_QUEUE_HH__ +#define __CPU_O3_CPU_INST_QUEUE_HH__ #include <list> #include <map> @@ -333,4 +333,4 @@ class InstructionQueue }; -#endif //__CPU_BETA_CPU_INST_QUEUE_HH__ +#endif //__CPU_O3_CPU_INST_QUEUE_HH__ diff --git a/cpu/o3/mem_dep_unit.hh b/cpu/o3/mem_dep_unit.hh index f2bb8923a..ca63577a1 100644 --- a/cpu/o3/mem_dep_unit.hh +++ b/cpu/o3/mem_dep_unit.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_MEM_DEP_UNIT_HH__ -#define __CPU_BETA_CPU_MEM_DEP_UNIT_HH__ +#ifndef __CPU_O3_CPU_MEM_DEP_UNIT_HH__ +#define __CPU_O3_CPU_MEM_DEP_UNIT_HH__ #include <map> #include <set> @@ -161,4 +161,4 @@ class MemDepUnit { Stats::Scalar<> conflictingStores; }; -#endif // __CPU_BETA_CPU_MEM_DEP_UNIT_HH__ +#endif // __CPU_O3_CPU_MEM_DEP_UNIT_HH__ diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh index d0891a7fb..bbc4162a6 100644 --- a/cpu/o3/ras.hh +++ b/cpu/o3/ras.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_RAS_HH__ -#define __CPU_BETA_CPU_RAS_HH__ +#ifndef __CPU_O3_CPU_RAS_HH__ +#define __CPU_O3_CPU_RAS_HH__ // For Addr type. #include "arch/alpha/isa_traits.hh" @@ -65,4 +65,4 @@ class ReturnAddrStack unsigned tos; }; -#endif // __CPU_BETA_CPU_RAS_HH__ +#endif // __CPU_O3_CPU_RAS_HH__ diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index e07944e67..e63b7fcfb 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_REGFILE_HH__ -#define __CPU_BETA_CPU_REGFILE_HH__ +#ifndef __CPU_O3_CPU_REGFILE_HH__ +#define __CPU_O3_CPU_REGFILE_HH__ // @todo: Destructor @@ -631,4 +631,4 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) #endif // #ifdef FULL_SYSTEM -#endif // __CPU_BETA_CPU_REGFILE_HH__ +#endif // __CPU_O3_CPU_REGFILE_HH__ diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh index 163177d87..a17ec7311 100644 --- a/cpu/o3/rename.hh +++ b/cpu/o3/rename.hh @@ -31,8 +31,8 @@ // May want to have different statuses to differentiate the different stall // conditions. -#ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__ -#define __CPU_BETA_CPU_SIMPLE_RENAME_HH__ +#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__ +#define __CPU_O3_CPU_SIMPLE_RENAME_HH__ #include <list> @@ -231,4 +231,4 @@ class SimpleRename Stats::Scalar<> renameValidUndoneMaps; }; -#endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__ +#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__ diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh index 48bb3db19..1469476ce 100644 --- a/cpu/o3/rename_map.hh +++ b/cpu/o3/rename_map.hh @@ -30,8 +30,8 @@ // Have it so that there's a more meaningful name given to the variable // that marks the beginning of the FP registers. -#ifndef __CPU_BETA_CPU_RENAME_MAP_HH__ -#define __CPU_BETA_CPU_RENAME_MAP_HH__ +#ifndef __CPU_O3_CPU_RENAME_MAP_HH__ +#define __CPU_O3_CPU_RENAME_MAP_HH__ #include <iostream> #include <utility> @@ -167,4 +167,4 @@ class SimpleRenameMap std::vector<bool> miscScoreboard; }; -#endif //__CPU_BETA_CPU_RENAME_MAP_HH__ +#endif //__CPU_O3_CPU_RENAME_MAP_HH__ diff --git a/cpu/o3/rob.cc b/cpu/o3/rob.cc index 7b590a6fe..c10f782fd 100644 --- a/cpu/o3/rob.cc +++ b/cpu/o3/rob.cc @@ -1,3 +1,30 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include "cpu/o3/alpha_dyn_inst.hh" #include "cpu/o3/alpha_impl.hh" diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh index b283e33ca..07ad75b52 100644 --- a/cpu/o3/rob.hh +++ b/cpu/o3/rob.hh @@ -32,8 +32,8 @@ // all instructions after the instruction, and all instructions after *and* // including that instruction. -#ifndef __CPU_BETA_CPU_ROB_HH__ -#define __CPU_BETA_CPU_ROB_HH__ +#ifndef __CPU_O3_CPU_ROB_HH__ +#define __CPU_O3_CPU_ROB_HH__ #include <utility> #include <vector> @@ -159,4 +159,4 @@ class ROB bool doneSquashing; }; -#endif //__CPU_BETA_CPU_ROB_HH__ +#endif //__CPU_O3_CPU_ROB_HH__ diff --git a/cpu/o3/rob_impl.hh b/cpu/o3/rob_impl.hh index 6dea46dfc..51f4afe75 100644 --- a/cpu/o3/rob_impl.hh +++ b/cpu/o3/rob_impl.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_ROB_IMPL_HH__ -#define __CPU_BETA_CPU_ROB_IMPL_HH__ +#ifndef __CPU_O3_CPU_ROB_IMPL_HH__ +#define __CPU_O3_CPU_ROB_IMPL_HH__ #include "cpu/o3/rob.hh" @@ -308,4 +308,4 @@ ROB<Impl>::readTailSeqNum() return (*tail)->seqNum; } -#endif // __CPU_BETA_CPU_ROB_IMPL_HH__ +#endif // __CPU_O3_CPU_ROB_IMPL_HH__ diff --git a/cpu/o3/sat_counter.hh b/cpu/o3/sat_counter.hh index 5455ca56a..e41430f5a 100644 --- a/cpu/o3/sat_counter.hh +++ b/cpu/o3/sat_counter.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_SAT_COUNTER_HH__ -#define __CPU_BETA_CPU_SAT_COUNTER_HH__ +#ifndef __CPU_O3_CPU_SAT_COUNTER_HH__ +#define __CPU_O3_CPU_SAT_COUNTER_HH__ #include "sim/host.hh" @@ -87,4 +87,4 @@ class SatCounter uint8_t counter; }; -#endif // __CPU_BETA_CPU_SAT_COUNTER_HH__ +#endif // __CPU_O3_CPU_SAT_COUNTER_HH__ diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh index 98a92791a..bcd590384 100644 --- a/cpu/o3/store_set.hh +++ b/cpu/o3/store_set.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_STORE_SET_HH__ -#define __CPU_BETA_CPU_STORE_SET_HH__ +#ifndef __CPU_O3_CPU_STORE_SET_HH__ +#define __CPU_O3_CPU_STORE_SET_HH__ #include <vector> @@ -83,4 +83,4 @@ class StoreSet int offset_bits; }; -#endif // __CPU_BETA_CPU_STORE_SET_HH__ +#endif // __CPU_O3_CPU_STORE_SET_HH__ diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh index feaede369..58ea1a7d9 100644 --- a/cpu/o3/tournament_pred.hh +++ b/cpu/o3/tournament_pred.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_BETA_CPU_TOURNAMENT_PRED_HH__ -#define __CPU_BETA_CPU_TOURNAMENT_PRED_HH__ +#ifndef __CPU_O3_CPU_TOURNAMENT_PRED_HH__ +#define __CPU_O3_CPU_TOURNAMENT_PRED_HH__ // For Addr type. #include "arch/alpha/isa_traits.hh" @@ -140,4 +140,4 @@ class TournamentBP unsigned threshold; }; -#endif // __CPU_BETA_CPU_TOURNAMENT_PRED_HH__ +#endif // __CPU_O3_CPU_TOURNAMENT_PRED_HH__ |