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-rw-r--r--cpu/base_dyn_inst.cc14
-rw-r--r--cpu/base_dyn_inst.hh18
-rw-r--r--cpu/exec_context.cc2
-rw-r--r--cpu/exec_context.hh32
-rw-r--r--cpu/o3/alpha_cpu.hh34
-rw-r--r--cpu/o3/alpha_cpu_impl.hh8
-rw-r--r--cpu/o3/alpha_dyn_inst.hh14
-rw-r--r--cpu/o3/alpha_dyn_inst_impl.hh8
-rw-r--r--cpu/o3/commit_impl.hh2
-rw-r--r--cpu/o3/fetch.hh2
-rw-r--r--cpu/o3/fetch_impl.hh6
-rw-r--r--cpu/o3/regfile.hh8
-rw-r--r--cpu/ozone/cpu.hh40
-rw-r--r--cpu/simple/cpu.cc48
-rw-r--r--cpu/simple/cpu.hh16
15 files changed, 126 insertions, 126 deletions
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 9901c90af..86314bef1 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -145,7 +145,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
fault = NoFault;
// note this is a local, not BaseDynInst::fault
- Fault * trans_fault = xc->translateDataReadReq(req);
+ Fault trans_fault = xc->translateDataReadReq(req);
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
// It's a valid address to cacheable space. Record key MemReq
@@ -208,14 +208,14 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
-Fault *
+Fault
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
MemReqPtr req = new MemReq(src, xc, 64);
req->asid = asid;
// translate to physical address
- Fault * fault = xc->translateDataReadReq(req);
+ Fault fault = xc->translateDataReadReq(req);
if (fault == NoFault) {
xc->copySrcAddr = src;
@@ -231,7 +231,7 @@ BaseDynInst<Impl>::copySrcTranslate(Addr src)
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
-Fault *
+Fault
BaseDynInst<Impl>::copy(Addr dest)
{
uint8_t data[64];
@@ -241,7 +241,7 @@ BaseDynInst<Impl>::copy(Addr dest)
req->asid = asid;
// translate to physical address
- Fault * fault = xc->translateDataWriteReq(req);
+ Fault fault = xc->translateDataWriteReq(req);
if (fault == NoFault) {
Addr dest_addr = req->paddr;
@@ -277,10 +277,10 @@ BaseDynInst<Impl>::dump(std::string &outstring)
#if 0
template <class Impl>
-Fault *
+Fault
BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
{
- Fault * fault;
+ Fault fault;
// check alignments, even speculative this test should always pass
if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index 84fd5403e..e94c44151 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -83,16 +83,16 @@ class BaseDynInst : public FastAlloc, public RefCounted
Trace::InstRecord *traceData;
template <class T>
- Fault * read(Addr addr, T &data, unsigned flags);
+ Fault read(Addr addr, T &data, unsigned flags);
template <class T>
- Fault * write(T data, Addr addr, unsigned flags,
+ Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
- Fault * copySrcTranslate(Addr src);
- Fault * copy(Addr dest);
+ Fault copySrcTranslate(Addr src);
+ Fault copy(Addr dest);
/** @todo: Consider making this private. */
public:
@@ -148,7 +148,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
ExecContext *xc;
/** The kind of fault this instruction has generated. */
- Fault * fault;
+ Fault fault;
/** The effective virtual address (lds & stores only). */
Addr effAddr;
@@ -219,7 +219,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
public:
void
- trace_mem(Fault * fault, // last fault
+ trace_mem(Fault fault, // last fault
MemCmd cmd, // last command
Addr addr, // virtual address of access
void *p, // memory accessed
@@ -232,7 +232,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
void dump(std::string &outstring);
/** Returns the fault type. */
- Fault * getFault() { return fault; }
+ Fault getFault() { return fault; }
/** Checks whether or not this instruction has had its branch target
* calculated yet. For now it is not utilized and is hacked to be
@@ -441,7 +441,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
template<class Impl>
template<class T>
-inline Fault *
+inline Fault
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
@@ -484,7 +484,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
template<class Impl>
template<class T>
-inline Fault *
+inline Fault
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
if (traceData) {
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index e7facbebb..9bed3ba47 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -221,7 +221,7 @@ ExecContext::regStats(const string &name)
}
void
-ExecContext::trap(Fault * fault)
+ExecContext::trap(Fault fault)
{
//TheISA::trap(fault); //One possible way to do it...
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 3fa7d078e..3e0d77254 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -213,17 +213,17 @@ class ExecContext
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@@ -238,7 +238,7 @@ class ExecContext
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
- Fault * dummyTranslation(MemReqPtr &req)
+ Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -249,15 +249,15 @@ class ExecContext
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return NoFault;
}
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@@ -265,7 +265,7 @@ class ExecContext
#endif
template <class T>
- Fault * read(MemReqPtr &req, T &data)
+ Fault read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@@ -275,14 +275,14 @@ class ExecContext
}
#endif
- Fault * error;
+ Fault error;
error = mem->read(req, data);
data = LittleEndianGuest::gtoh(data);
return error;
}
template <class T>
- Fault * write(MemReqPtr &req, T &data)
+ Fault write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@@ -340,7 +340,7 @@ class ExecContext
inst = new_inst;
}
- Fault * instRead(MemReqPtr &req)
+ Fault instRead(MemReqPtr &req)
{
return mem->read(req, inst);
}
@@ -419,13 +419,13 @@ class ExecContext
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
- Fault * hwrei();
+ Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
- void ev5_trap(Fault * fault);
+ void ev5_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif
@@ -435,7 +435,7 @@ class ExecContext
* @todo How to do this properly so it's dependent upon ISA only?
*/
- void trap(Fault * fault);
+ void trap(Fault fault);
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 2be70f5c2..b35bcf9e3 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -63,23 +63,23 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// void clear_interrupt(int int_num, int index);
// void clear_interrupts();
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
#else
- Fault * dummyTranslation(MemReqPtr &req)
+ Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -91,17 +91,17 @@ class AlphaFullCPU : public FullO3CPU<Impl>
return NoFault;
}
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@@ -136,16 +136,16 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// look like.
#if FULL_SYSTEM
uint64_t *getIpr();
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
int readIntrFlag();
void setIntrFlag(int val);
- Fault * hwrei();
+ Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
bool inPalMode(uint64_t PC)
{ return AlphaISA::PcPAL(PC); }
- void trap(Fault * fault);
+ void trap(Fault fault);
bool simPalCheck(int palFunc);
void processInterrupts();
@@ -198,7 +198,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
bool palShadowEnabled;
// Not sure this is used anywhere.
- void intr_post(RegFile *regs, Fault * fault, Addr pc);
+ void intr_post(RegFile *regs, Fault fault, Addr pc);
// Actually used within exec files. Implement properly.
void swapPALShadow(bool use_shadow);
// Called by CPU constructor. Can implement as I please.
@@ -211,7 +211,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
template <class T>
- Fault * read(MemReqPtr &req, T &data)
+ Fault read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@@ -221,20 +221,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
#endif
- Fault * error;
+ Fault error;
error = this->mem->read(req, data);
data = gtoh(data);
return error;
}
template <class T>
- Fault * read(MemReqPtr &req, T &data, int load_idx)
+ Fault read(MemReqPtr &req, T &data, int load_idx)
{
return this->iew.ldstQueue.read(req, data, load_idx);
}
template <class T>
- Fault * write(MemReqPtr &req, T &data)
+ Fault write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@@ -284,7 +284,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
template <class T>
- Fault * write(MemReqPtr &req, T &data, int store_idx)
+ Fault write(MemReqPtr &req, T &data, int store_idx)
{
return this->iew.ldstQueue.write(req, data, store_idx);
}
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 6736cf9bc..7ec1ba663 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr()
template <class Impl>
uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault)
+AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
{
return this->regFile.readIpr(idx, fault);
}
template <class Impl>
-Fault *
+Fault
AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
{
return this->regFile.setIpr(idx, val);
@@ -274,7 +274,7 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
// Can force commit stage to squash and stuff.
template <class Impl>
-Fault *
+Fault
AlphaFullCPU<Impl>::hwrei()
{
uint64_t *ipr = getIpr();
@@ -323,7 +323,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
// stage.
template <class Impl>
void
-AlphaFullCPU<Impl>::trap(Fault * fault)
+AlphaFullCPU<Impl>::trap(Fault fault)
{
// Keep in mind that a trap may be initiated by fetch if there's a TLB
// miss
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index b113d9487..f282c287c 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -69,7 +69,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
AlphaDynInst(StaticInstPtr &_staticInst);
/** Executes the instruction.*/
- Fault * execute()
+ Fault execute()
{
return this->fault = this->staticInst->execute(this, this->traceData);
}
@@ -82,13 +82,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setFpcr(uint64_t val);
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
- Fault * hwrei();
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
+ Fault hwrei();
int readIntrFlag();
void setIntrFlag(int val);
bool inPalMode();
- void trap(Fault * fault);
+ void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
void syscall();
@@ -215,12 +215,12 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
- Fault * calcEA()
+ Fault calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
- Fault * memAccess()
+ Fault memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index 9f9df3da1..eebe7675a 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -98,20 +98,20 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
#if FULL_SYSTEM
template <class Impl>
uint64_t
-AlphaDynInst<Impl>::readIpr(int idx, Fault * &fault)
+AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
{
return this->cpu->readIpr(idx, fault);
}
template <class Impl>
-Fault *
+Fault
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
{
return this->cpu->setIpr(idx, val);
}
template <class Impl>
-Fault *
+Fault
AlphaDynInst<Impl>::hwrei()
{
return this->cpu->hwrei();
@@ -140,7 +140,7 @@ AlphaDynInst<Impl>::inPalMode()
template <class Impl>
void
-AlphaDynInst<Impl>::trap(Fault * fault)
+AlphaDynInst<Impl>::trap(Fault fault)
{
this->cpu->trap(fault);
}
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index 47b4dfd00..e289bc0c0 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -393,7 +393,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
}
// Check if the instruction caused a fault. If so, trap.
- Fault * inst_fault = head_inst->getFault();
+ Fault inst_fault = head_inst->getFault();
if (inst_fault != NoFault) {
if (!head_inst->isNop()) {
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 82a6cd818..cc64800d9 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -122,7 +122,7 @@ class SimpleFetch
* @param fetch_PC The PC address that is being fetched from.
* @return Any fault that occured.
*/
- Fault * fetchCacheLine(Addr fetch_PC);
+ Fault fetchCacheLine(Addr fetch_PC);
inline void doSquash(const Addr &new_PC);
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index e8d333ed4..8029fc732 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -221,7 +221,7 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
}
template <class Impl>
-Fault *
+Fault
SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
{
// Check if the instruction exists within the cache.
@@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
unsigned flags = 0;
#endif // FULL_SYSTEM
- Fault * fault = NoFault;
+ Fault fault = NoFault;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
@@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
Addr fetch_PC = cpu->readPC();
// Fault code for memory access.
- Fault * fault = NoFault;
+ Fault fault = NoFault;
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 021f9b0b6..ee7b8858e 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -215,8 +215,8 @@ class PhysRegFile
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
@@ -279,7 +279,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
//the DynInst level.
template <class Impl>
uint64_t
-PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
+PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
{
uint64_t retval = 0; // return value, default 0
@@ -387,7 +387,7 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
extern int break_ipl;
template <class Impl>
-Fault *
+Fault
PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
{
uint64_t old;
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 7976632d9..667e2b3f8 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -285,17 +285,17 @@ class OoOCPU : public BaseCPU
int getInstAsid() { return xc->regs.instAsid(); }
int getDataAsid() { return xc->regs.dataAsid(); }
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@@ -310,7 +310,7 @@ class OoOCPU : public BaseCPU
int getInstAsid() { return xc->asid; }
int getDataAsid() { return xc->asid; }
- Fault * dummyTranslation(MemReqPtr &req)
+ Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -321,15 +321,15 @@ class OoOCPU : public BaseCPU
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return NoFault;
}
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@@ -337,10 +337,10 @@ class OoOCPU : public BaseCPU
#endif
template <class T>
- Fault * read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
+ Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
template <class T>
- Fault * write(T data, Addr addr, unsigned flags,
+ Fault write(T data, Addr addr, unsigned flags,
uint64_t *res, DynInstPtr inst);
void prefetch(Addr addr, unsigned flags)
@@ -353,9 +353,9 @@ class OoOCPU : public BaseCPU
// need to do this...
}
- Fault * copySrcTranslate(Addr src);
+ Fault copySrcTranslate(Addr src);
- Fault * copy(Addr dest);
+ Fault copy(Addr dest);
private:
bool executeInst(DynInstPtr &inst);
@@ -368,7 +368,7 @@ class OoOCPU : public BaseCPU
bool getOneInst();
- Fault * fetchCacheLine();
+ Fault fetchCacheLine();
InstSeqNum getAndIncrementInstSeq();
@@ -511,13 +511,13 @@ class OoOCPU : public BaseCPU
void setFpcr(uint64_t val) { xc->setFpcr(val); }
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
- Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
- Fault * hwrei() { return xc->hwrei(); }
+ uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
+ Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
+ Fault hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
- void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
+ void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
@@ -530,7 +530,7 @@ class OoOCPU : public BaseCPU
// precise architected memory state accessor macros
template <class Impl>
template <class T>
-Fault *
+Fault
OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
{
MemReqPtr readReq = new MemReq();
@@ -541,7 +541,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
readReq->reset(addr, sizeof(T), flags);
// translate to physical address - This might be an ISA impl call
- Fault * fault = translateDataReadReq(readReq);
+ Fault fault = translateDataReadReq(readReq);
// do functional access
if (fault == NoFault)
@@ -575,7 +575,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
template <class Impl>
template <class T>
-Fault *
+Fault
OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
uint64_t *res, DynInstPtr inst)
{
@@ -594,7 +594,7 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
writeReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault * fault = translateDataWriteReq(writeReq);
+ Fault fault = translateDataWriteReq(writeReq);
// do functional access
if (fault == NoFault)
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index c3f256de9..f7a6d2c21 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -312,7 +312,7 @@ change_thread_state(int thread_number, int activate, int priority)
{
}
-Fault *
+Fault
SimpleCPU::copySrcTranslate(Addr src)
{
static bool no_warn = true;
@@ -332,7 +332,7 @@ SimpleCPU::copySrcTranslate(Addr src)
memReq->reset(src & ~(blk_size - 1), blk_size);
// translate to physical address
- Fault * fault = xc->translateDataReadReq(memReq);
+ Fault fault = xc->translateDataReadReq(memReq);
assert(fault != AlignmentFault);
@@ -346,7 +346,7 @@ SimpleCPU::copySrcTranslate(Addr src)
return fault;
}
-Fault *
+Fault
SimpleCPU::copy(Addr dest)
{
static bool no_warn = true;
@@ -367,7 +367,7 @@ SimpleCPU::copy(Addr dest)
memReq->reset(dest & ~(blk_size -1), blk_size);
// translate to physical address
- Fault * fault = xc->translateDataWriteReq(memReq);
+ Fault fault = xc->translateDataWriteReq(memReq);
assert(fault != AlignmentFault);
@@ -394,11 +394,11 @@ SimpleCPU::copy(Addr dest)
// precise architected memory state accessor macros
template <class T>
-Fault *
+Fault
SimpleCPU::read(Addr addr, T &data, unsigned flags)
{
if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
- Fault * fault = xc->read(memReq,data);
+ Fault fault = xc->read(memReq,data);
if (traceData) {
traceData->setAddr(addr);
@@ -409,7 +409,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault * fault = xc->translateDataReadReq(memReq);
+ Fault fault = xc->translateDataReadReq(memReq);
// if we have a cache, do cache access too
if (fault == NoFault && dcacheInterface) {
@@ -447,32 +447,32 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
-Fault *
+Fault
SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
template
-Fault *
+Fault
SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
template
-Fault *
+Fault
SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
template
-Fault *
+Fault
SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
#endif //DOXYGEN_SHOULD_SKIP_THIS
template<>
-Fault *
+Fault
SimpleCPU::read(Addr addr, double &data, unsigned flags)
{
return read(addr, *(uint64_t*)&data, flags);
}
template<>
-Fault *
+Fault
SimpleCPU::read(Addr addr, float &data, unsigned flags)
{
return read(addr, *(uint32_t*)&data, flags);
@@ -480,7 +480,7 @@ SimpleCPU::read(Addr addr, float &data, unsigned flags)
template<>
-Fault *
+Fault
SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
{
return read(addr, (uint32_t&)data, flags);
@@ -488,13 +488,13 @@ SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
template <class T>
-Fault *
+Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault * fault = xc->translateDataWriteReq(memReq);
+ Fault fault = xc->translateDataWriteReq(memReq);
// do functional access
if (fault == NoFault)
@@ -531,32 +531,32 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
-Fault *
+Fault
SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
template
-Fault *
+Fault
SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
template
-Fault *
+Fault
SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
template
-Fault *
+Fault
SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
#endif //DOXYGEN_SHOULD_SKIP_THIS
template<>
-Fault *
+Fault
SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
{
return write(*(uint64_t*)&data, addr, flags, res);
}
template<>
-Fault *
+Fault
SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
{
return write(*(uint32_t*)&data, addr, flags, res);
@@ -564,7 +564,7 @@ SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
template<>
-Fault *
+Fault
SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
{
return write((uint32_t)data, addr, flags, res);
@@ -638,7 +638,7 @@ SimpleCPU::tick()
traceData = NULL;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
#if FULL_SYSTEM
if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 8a3900726..d3e0323b6 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -236,10 +236,10 @@ class SimpleCPU : public BaseCPU
virtual void unserialize(Checkpoint *cp, const std::string &section);
template <class T>
- Fault * read(Addr addr, T &data, unsigned flags);
+ Fault read(Addr addr, T &data, unsigned flags);
template <class T>
- Fault * write(T data, Addr addr, unsigned flags, uint64_t *res);
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
@@ -256,9 +256,9 @@ class SimpleCPU : public BaseCPU
// need to do this...
}
- Fault * copySrcTranslate(Addr src);
+ Fault copySrcTranslate(Addr src);
- Fault * copy(Addr dest);
+ Fault copy(Addr dest);
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
@@ -327,13 +327,13 @@ class SimpleCPU : public BaseCPU
void setFpcr(uint64_t val) { xc->setFpcr(val); }
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
- Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
- Fault * hwrei() { return xc->hwrei(); }
+ uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
+ Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
+ Fault hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
- void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
+ void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 01:45:34 +0000