diff options
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/exec_context.hh | 3 | ||||
-rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 2 | ||||
-rw-r--r-- | cpu/simple_cpu/simple_cpu.hh | 50 | ||||
-rw-r--r-- | cpu/static_inst.hh | 10 |
4 files changed, 59 insertions, 6 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index f2f2c0879..7be83539a 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -387,7 +387,10 @@ class ExecContext #ifdef FULL_SYSTEM uint64_t readIpr(int idx, Fault &fault); Fault setIpr(int idx, uint64_t val); + int readIntrFlag() { return regs.intrflag; } + void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); + bool inPalMode() { return PC_PAL(regs.pc); } void ev5_trap(Fault fault); bool simPalCheck(int palFunc); #endif diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index f29d9d60e..065140883 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -714,7 +714,7 @@ SimpleCPU::tick() xc->func_exe_inst++; - fault = si->execute(this, xc, traceData); + fault = si->execute(this, traceData); #ifdef FULL_SYSTEM SWContext *ctx = xc->swCtx; diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index d634753b9..4977e6992 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -250,6 +250,56 @@ class SimpleCPU : public BaseCPU Fault copySrcTranslate(Addr src); Fault copy(Addr dest); + + uint64_t readIntReg(int reg_idx) { return xc->readIntReg(reg_idx); } + + float readFloatRegSingle(int reg_idx) + { return xc->readFloatRegSingle(reg_idx); } + + double readFloatRegDouble(int reg_idx) + { return xc->readFloatRegDouble(reg_idx); } + + uint64_t readFloatRegInt(int reg_idx) + { return xc->readFloatRegInt(reg_idx); } + + void setIntReg(int reg_idx, uint64_t val) + { return xc->setIntReg(reg_idx, val); } + + void setFloatRegSingle(int reg_idx, float val) + { return xc->setFloatRegSingle(reg_idx, val); } + + void setFloatRegDouble(int reg_idx, double val) + { return xc->setFloatRegDouble(reg_idx, val); } + + void setFloatRegInt(int reg_idx, uint64_t val) + { return xc->setFloatRegInt(reg_idx, val); } + + uint64_t readPC() { return xc->readPC(); } + void setNextPC(uint64_t val) { return xc->setNextPC(val); } + + uint64_t readUniq() { return xc->readUniq(); } + void setUniq(uint64_t val) { return xc->setUniq(val); } + + uint64_t readFpcr() { return xc->readFpcr(); } + void setFpcr(uint64_t val) { return xc->setFpcr(val); } + +#ifdef FULL_SYSTEM + uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } + Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } + Fault hwrei() { return xc->hwrei(); } + int readIntrFlag() { return xc->readIntrFlag(); } + void setIntrFlag(int val) { xc->setIntrFlag(val); } + bool inPalMode() { return xc->inPalMode(); } + void ev5_trap(Fault fault) { return xc->ev5_trap(fault); } + bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } +#else + void syscall() { xc->syscall(); } +#endif + + bool misspeculating() { return xc->misspeculating(); } + ExecContext *xcBase() { return xc; } }; +typedef SimpleCPU SimpleCPUExecContext; + #endif // __SIMPLE_CPU_HH__ diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index cdf9aefa0..57208f8e6 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -41,10 +41,10 @@ // forward declarations class ExecContext; -class SpecExecContext; -class SimpleCPU; -class FullCPU; class DynInst; +typedef DynInst FullCPUExecContext; +class SimpleCPU; +typedef SimpleCPU SimpleCPUExecContext; class SymbolTable; namespace Trace { @@ -307,13 +307,13 @@ class StaticInst : public StaticInstBase /** * Execute this instruction under SimpleCPU model. */ - virtual Fault execute(SimpleCPU *cpu, ExecContext *xc, + virtual Fault execute(SimpleCPUExecContext *xc, Trace::InstRecord *traceData) = 0; /** * Execute this instruction under detailed FullCPU model. */ - virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, + virtual Fault execute(FullCPUExecContext *xc, Trace::InstRecord *traceData) = 0; /** |