diff options
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/base_dyn_inst.cc | 7 | ||||
-rw-r--r-- | cpu/exec_context.cc | 4 | ||||
-rw-r--r-- | cpu/exec_context.hh | 4 | ||||
-rw-r--r-- | cpu/o3/alpha_cpu.hh | 2 | ||||
-rw-r--r-- | cpu/o3/alpha_cpu_builder.cc | 4 | ||||
-rw-r--r-- | cpu/o3/alpha_cpu_impl.hh | 16 | ||||
-rw-r--r-- | cpu/o3/bpred_unit.hh | 2 | ||||
-rw-r--r-- | cpu/o3/comm.hh | 2 | ||||
-rw-r--r-- | cpu/o3/cpu.hh | 2 | ||||
-rw-r--r-- | cpu/o3/regfile.hh | 14 | ||||
-rw-r--r-- | cpu/ozone/cpu_impl.hh | 2 | ||||
-rw-r--r-- | cpu/ozone/ea_list.cc | 2 | ||||
-rw-r--r-- | cpu/ozone/ea_list.hh | 2 | ||||
-rw-r--r-- | cpu/profile.hh | 2 | ||||
-rw-r--r-- | cpu/simple/cpu.cc | 14 | ||||
-rw-r--r-- | cpu/simple/cpu.hh | 2 |
16 files changed, 41 insertions, 40 deletions
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index 86314bef1..5905cdad2 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -36,7 +36,7 @@ #include "base/cprintf.hh" #include "base/trace.hh" -#include "arch/alpha/faults.hh" +#include "arch/faults.hh" #include "cpu/exetrace.hh" #include "mem/mem_req.hh" @@ -45,6 +45,7 @@ #include "cpu/o3/alpha_cpu.hh" using namespace std; +using namespace TheISA; #define NOHASH #ifndef NOHASH @@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars() asid = 0; // Initialize the fault to be unimplemented opcode. - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; ++instcount; @@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) break; default: - fault = MachineCheckFault; + fault = genMachineCheckFault(); break; } diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc index 9bed3ba47..7e8b81e18 100644 --- a/cpu/exec_context.cc +++ b/cpu/exec_context.cc @@ -40,7 +40,7 @@ #include "sim/serialize.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" #else #include "sim/process.hh" #endif @@ -227,7 +227,7 @@ ExecContext::trap(Fault fault) /** @todo: Going to hack it for now. Do a true fixup later. */ #if FULL_SYSTEM - ev5_trap(fault); + fault->ev5_trap(this); #else fatal("fault (%d) detected @ PC 0x%08p", fault, readPC()); #endif diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 3e0d77254..e23370d0b 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -46,7 +46,7 @@ class BaseCPU; #if FULL_SYSTEM #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" +#include "arch/tlb.hh" class FunctionProfile; class ProfileNode; @@ -425,7 +425,7 @@ class ExecContext void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } - void ev5_trap(Fault fault); + void ev5_temp_trap(Fault fault); bool simPalCheck(int palFunc); #endif diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index b35bcf9e3..ea0aae41f 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -280,7 +280,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> #endif - return this->mem->write(req, (T)::htog(data)); + return this->mem->write(req, (T)htog(data)); } template <class T> diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 3547fb1b5..95d2f8f37 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -50,8 +50,8 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 7ec1ba663..9b7cd8a0e 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -280,7 +280,7 @@ AlphaFullCPU<Impl>::hwrei() uint64_t *ipr = getIpr(); if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); @@ -329,21 +329,21 @@ AlphaFullCPU<Impl>::trap(Fault fault) // miss uint64_t PC = this->commit.readCommitPC(); - DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name"); - this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name")); + DPRINTF(Fault, "Fault %s\n", fault->name()); + this->recordEvent(csprintf("Fault %s", fault->name())); -// kernelStats.fault(fault); + //kernelStats.fault(fault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("Arithmetic traps are unimplemented!"); AlphaISA::InternalProcReg *ipr = getIpr(); // exception restart address - Get the commit PC - if (fault != InterruptFault || !inPalMode(PC)) + if (!fault->isA<InterruptFault>() || !inPalMode(PC)) ipr[AlphaISA::IPR_EXC_ADDR] = PC; - if (fault == PalFault || fault == ArithmeticFault /* || + if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* || fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction ipr[AlphaISA::IPR_EXC_ADDR] += 4; @@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault) swapPALShadow(true); this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + - AlphaISA::fault_addr(fault) ); + (dynamic_cast<AlphaFault *>(fault.get()))->vect()); this->regFile.setNextPC(PC + sizeof(MachInst)); } diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index 0a77b83dc..2725684f7 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -30,7 +30,7 @@ #define __BPRED_UNIT_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index e4de1d304..c74c77ddf 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -31,7 +31,7 @@ #include <vector> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 321d61dce..802860ab5 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -50,7 +50,7 @@ #include "sim/process.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" using namespace EV5; #endif diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index ee7b8858e..3bf96a37b 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -31,14 +31,14 @@ // @todo: Destructor -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/faults.hh" +#include "arch/isa_traits.hh" +#include "arch/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" #include "kern/kernel_stats.hh" using namespace EV5; @@ -372,12 +372,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault) case TheISA::IPR_DTB_IAP: case TheISA::IPR_ITB_IA: case TheISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; default: // invalid IPR - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; } @@ -525,7 +525,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) case TheISA::IPR_ITB_PTE_TEMP: case TheISA::IPR_DTB_PTE_TEMP: // read-only registers - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; case TheISA::IPR_HWINT_CLR: case TheISA::IPR_SL_XMIT: @@ -627,7 +627,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) default: // invalid IPR - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } // no error... diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 009a81b98..e7ed3cfe0 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -29,7 +29,7 @@ #ifndef __CPU_OOO_CPU_OOO_IMPL_HH__ #define __CPU_OOO_CPU_OOO_IMPL_HH__ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" template <class Impl> class OoOCPU; diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc index 80cf80fb8..6114a0ca1 100644 --- a/cpu/ozone/ea_list.cc +++ b/cpu/ozone/ea_list.cc @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "cpu/ooo_cpu/ea_list.hh" diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh index def7e67d5..c0eee4bb8 100644 --- a/cpu/ozone/ea_list.hh +++ b/cpu/ozone/ea_list.hh @@ -32,7 +32,7 @@ #include <list> #include <utility> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" /** diff --git a/cpu/profile.hh b/cpu/profile.hh index 18061f9bf..1eb012a27 100644 --- a/cpu/profile.hh +++ b/cpu/profile.hh @@ -33,7 +33,7 @@ #include "cpu/static_inst.hh" #include "sim/host.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" class ProfileNode { diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 944bdbb0a..1f362876f 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -67,9 +67,9 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/stacktrace.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/stacktrace.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM @@ -347,7 +347,7 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(memReq); - assert(fault != AlignmentFault); + assert(!fault->isAlignmentFault()); if (fault == NoFault) { xc->copySrcAddr = src; @@ -382,7 +382,7 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(memReq); - assert(fault != AlignmentFault); + assert(!fault->isAlignmentFault()); if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; @@ -688,7 +688,7 @@ SimpleCPU::tick() if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { ipr[IPR_ISR] = summary; ipr[IPR_INTID] = ipl; - xc->ev5_trap(InterruptFault); + (new InterruptFault)->ev5_trap(xc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[IPR_IPLR], ipl, summary); @@ -812,7 +812,7 @@ SimpleCPU::tick() if (fault != NoFault) { #if FULL_SYSTEM - xc->ev5_trap(fault); + fault->ev5_trap(xc); #else // !FULL_SYSTEM fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); #endif // FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index ed7b1e29b..c58b3c5ba 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -334,7 +334,7 @@ class SimpleCPU : public BaseCPU int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { xc->ev5_trap(fault); } + void ev5_trap(Fault fault) { fault->ev5_trap(xc); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } |