3 files changed, 115 insertions, 1 deletions
diff --git a/cpu/op_class.cc b/cpu/op_class.cc
new file mode 100644
index 000000000..00136ded5
--- /dev/null
+++ b/cpu/op_class.cc
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/op_class.hh"
+
+/** OpClass enum -> description string */
+const char *
+opClassStrings[Num_OpClasses] =
+{
+    "(null)",
+    "IntAlu",
+    "IntMult",
+    "IntDiv",
+    "FloatAdd",
+    "FloatCmp",
+    "FloatCvt",
+    "FloatMult",
+    "FloatDiv",
+    "FloatSqrt",
+    "MemRead",
+    "MemWrite",
+    "IprAccess",
+    "InstPrefetch"
+};
+
diff --git a/cpu/op_class.hh b/cpu/op_class.hh
new file mode 100644
index 000000000..cdb40a0fb
--- /dev/null
+++ b/cpu/op_class.hh
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU__OP_CLASS_HH__
+#define __CPU__OP_CLASS_HH__
+
+/**
+ * @file
+ * Definition of operation classes.
+ */
+
+/**
+ * Instruction operation classes.  These classes are used for
+ * assigning instructions to functional units.
+ */
+enum OpClass {
+    No_OpClass = 0,	///< Instruction does not use a functional unit
+    IntAluOp,		///< Integer ALU operaton (add/sub/logical)
+    IntMultOp,		///< Integer multiply
+    IntDivOp,		///< Integer divide
+    FloatAddOp,		///< Floating point add/subtract
+    FloatCmpOp,		///< Floating point comparison
+    FloatCvtOp,		///< Floating point<->integer conversion
+    FloatMultOp,	///< Floating point multiply
+    FloatDivOp,		///< Floating point divide
+    FloatSqrtOp,	///< Floating point square root
+    MemReadOp,		///< Memory read port
+    MemWriteOp,		///< Memory write port
+    IprAccessOp,	///< Internal Processor Register read/write port
+    InstPrefetchOp,	///< Instruction prefetch port (on I-cache)
+    Num_OpClasses	///< Total number of operation classes
+};
+
+/**
+ * Array mapping OpClass enum values to strings.  Defined in op_class.cc.
+ */
+extern const char *opClassStrings[];
+
+#endif // __CPU__OP_CLASS_HH__
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 85cfb5ae7..09eb7efbf 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -34,7 +34,7 @@
 
 #include "base/hashmap.hh"
 #include "base/refcnt.hh"
-#include "encumbered/cpu/full/op_class.hh"
+#include "cpu/op_class.hh"
 #include "sim/host.hh"
 #include "targetarch/isa_traits.hh"