1 files changed, 17 insertions, 9 deletions

diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index f2bce33ca..7f4acea1c 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -78,33 +78,35 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
 
     switch(size) {
       case sizeof(uint32_t):
-        memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t));
+        memcpy(data, &config.data[offset], sizeof(uint32_t));
         *(uint32_t*)data = htoa(*(uint32_t*)data);
+
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
                 params()->deviceNum, params()->functionNum, offset, size,
-                *(uint32_t*)(config.data + offset));
+                *(uint32_t*)data);
         break;
 
       case sizeof(uint16_t):
-        memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t));
+        memcpy(data, &config.data[offset], sizeof(uint16_t));
         *(uint16_t*)data = htoa(*(uint16_t*)data);
+
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
                 params()->deviceNum, params()->functionNum, offset, size,
-                *(uint16_t*)(config.data + offset));
+                *(uint16_t*)data);
         break;
 
       case sizeof(uint8_t):
-        memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
+        memcpy(data, &config.data[offset], sizeof(uint8_t));
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
                 params()->deviceNum, params()->functionNum, offset, size,
-                (uint16_t)(*(uint8_t*)(config.data + offset)));
+                *data);
         break;
 
       default:
-        panic("Invalid Read Size");
+        panic("Invalid PCI configuration read size!\n");
     }
 }
 
@@ -138,7 +140,13 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
           case PCI_LATENCY_TIMER:
             *(uint8_t *)&config.data[offset] = htoa(byte_value);
             break;
-
+          /* Do nothing for these read-only registers */
+          case PCI0_INTERRUPT_PIN:
+          case PCI0_MINIMUM_GRANT:
+          case PCI0_MAXIMUM_LATENCY:
+          case PCI_CLASS_CODE:
+          case PCI_REVISION_ID:
+            break;
           default:
             panic("writing to a read only register");
         }
@@ -192,7 +200,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
                         htoa((word_value & ~0x3) |
                         (htoa(config.data[offset]) & 0x3));
 
-                    if (word_value & ~0x1) {
+                    if (word_value != 0x1) {
                         Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
                         Addr base_size = BARSize[barnum];