1 files changed, 60 insertions, 10 deletions

diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index ba49c361b..a64f643a2 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -1,4 +1,30 @@
-/* $Id$ */
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 /* @file
  * Emulation of the Tsunami CChip CSRs
@@ -9,21 +35,23 @@
 #include <vector>
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
 #include "dev/console.hh"
 #include "dev/tsunami_cchip.hh"
 #include "dev/tsunamireg.h"
 #include "dev/tsunami.hh"
-#include "cpu/intr_control.hh"
+#include "mem/bus/bus.hh"
+#include "mem/bus/pio_interface.hh"
+#include "mem/bus/pio_interface_impl.hh"
 #include "mem/functional_mem/memory_control.hh"
+#include "cpu/intr_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 
 TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
-                           MemoryController *mmu)
-    : FunctionalMemory(name), addr(a), tsunami(t)
+                           MemoryController *mmu, HierParams *hier, Bus* bus)
+    : PioDevice(name), addr(a), tsunami(t)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
 
@@ -35,6 +63,12 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
         RTCInterrupting[i] = false;
     }
 
+    if (bus) {
+        pioInterface = newPioInterface(name, hier, bus, this,
+                                      &TsunamiCChip::cacheAccess);
+        pioInterface->addAddrRange(addr, addr + size - 1);
+    }
+
     drir = 0;
     misc = 0;
 
@@ -68,7 +102,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
               case TSDEV_CC_AAR1:
               case TSDEV_CC_AAR2:
               case TSDEV_CC_AAR3:
-                  panic("TSDEV_CC_AARx not implemeted\n");
+                  *(uint64_t*)data = 0;
                   return No_Fault;
               case TSDEV_CC_DIM0:
                   *(uint64_t*)data = dim[0];
@@ -131,8 +165,8 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
 Fault
 TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 {
-    DPRINTF(Tsunami, "write - va=%#x size=%d \n",
-            req->vaddr, req->size);
+    DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
+            req->vaddr, *(uint64_t*)data, req->size);
 
     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
 
@@ -195,6 +229,11 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
                     }
                     supportedWrite = true;
                 }
+
+        // ignore NXMs
+        if (*(uint64_t*)data & 0x10000000)
+            supportedWrite = true;
+
                 if(!supportedWrite) panic("TSDEV_CC_MISC write not implemented\n");
                 return No_Fault;
               case TSDEV_CC_AAR0:
@@ -342,6 +381,13 @@ TsunamiCChip::clearDRIR(uint32_t interrupt)
         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 }
 
+Tick
+TsunamiCChip::cacheAccess(MemReqPtr &req)
+{
+    return curTick + 1000;
+}
+
+
 void
 TsunamiCChip::serialize(std::ostream &os)
 {
@@ -371,6 +417,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
     SimObjectParam<Tsunami *> tsunami;
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
+    SimObjectParam<Bus*> io_bus;
+    SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 
@@ -378,13 +426,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 
     INIT_PARAM(tsunami, "Tsunami"),
     INIT_PARAM(mmu, "Memory Controller"),
-    INIT_PARAM(addr, "Device Address")
+    INIT_PARAM(addr, "Device Address"),
+    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 
 CREATE_SIM_OBJECT(TsunamiCChip)
 {
-    return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu);
+    return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
 }
 
 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)