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-rw-r--r--dev/tsunami_pchip.cc386
1 files changed, 178 insertions, 208 deletions
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index 46efc3dfe..1323a0548 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -38,11 +38,7 @@
#include "dev/tsunami_pchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
+#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@@ -50,12 +46,10 @@ using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
-TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
- MemoryController *mmu, HierParams *hier,
- Bus *pio_bus, Tick pio_latency)
- : PioDevice(name, t), addr(a), tsunami(t)
+TsunamiPChip::TsunamiPChip(Params *p)
+: BasicPioDevice(p)
{
- mmu->add_child(this, RangeSize(addr, size));
+ pioSize = 0xfff;
for (int i = 0; i < 4; i++) {
wsba[i] = 0;
@@ -63,195 +57,175 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
tba[i] = 0;
}
- if (pio_bus) {
- pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
- &TsunamiPChip::cacheAccess);
- pioInterface->addAddrRange(RangeSize(addr, size));
- pioLatency = pio_latency * pio_bus->clockRate;
- }
-
-
// initialize pchip control register
pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
//Set back pointer in tsunami
- tsunami->pchip = this;
+ p->tsunami->pchip = this;
}
-Fault
-TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
+Tick
+TsunamiPChip::read(Packet &pkt)
{
- DPRINTF(Tsunami, "read va=%#x size=%d\n",
- req->vaddr, req->size);
-
- Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
-
- switch (req->size) {
-
- case sizeof(uint64_t):
- switch(daddr) {
- case TSDEV_PC_WSBA0:
- *(uint64_t*)data = wsba[0];
- return NoFault;
- case TSDEV_PC_WSBA1:
- *(uint64_t*)data = wsba[1];
- return NoFault;
- case TSDEV_PC_WSBA2:
- *(uint64_t*)data = wsba[2];
- return NoFault;
- case TSDEV_PC_WSBA3:
- *(uint64_t*)data = wsba[3];
- return NoFault;
- case TSDEV_PC_WSM0:
- *(uint64_t*)data = wsm[0];
- return NoFault;
- case TSDEV_PC_WSM1:
- *(uint64_t*)data = wsm[1];
- return NoFault;
- case TSDEV_PC_WSM2:
- *(uint64_t*)data = wsm[2];
- return NoFault;
- case TSDEV_PC_WSM3:
- *(uint64_t*)data = wsm[3];
- return NoFault;
- case TSDEV_PC_TBA0:
- *(uint64_t*)data = tba[0];
- return NoFault;
- case TSDEV_PC_TBA1:
- *(uint64_t*)data = tba[1];
- return NoFault;
- case TSDEV_PC_TBA2:
- *(uint64_t*)data = tba[2];
- return NoFault;
- case TSDEV_PC_TBA3:
- *(uint64_t*)data = tba[3];
- return NoFault;
- case TSDEV_PC_PCTL:
- *(uint64_t*)data = pctl;
- return NoFault;
- case TSDEV_PC_PLAT:
- panic("PC_PLAT not implemented\n");
- case TSDEV_PC_RES:
- panic("PC_RES not implemented\n");
- case TSDEV_PC_PERROR:
- *(uint64_t*)data = 0x00;
- return NoFault;
- case TSDEV_PC_PERRMASK:
- *(uint64_t*)data = 0x00;
- return NoFault;
- case TSDEV_PC_PERRSET:
- panic("PC_PERRSET not implemented\n");
- case TSDEV_PC_TLBIV:
- panic("PC_TLBIV not implemented\n");
- case TSDEV_PC_TLBIA:
- *(uint64_t*)data = 0x00; // shouldn't be readable, but linux
- return NoFault;
- case TSDEV_PC_PMONCTL:
- panic("PC_PMONCTL not implemented\n");
- case TSDEV_PC_PMONCNT:
- panic("PC_PMONCTN not implemented\n");
- default:
- panic("Default in PChip Read reached reading 0x%x\n", daddr);
-
- } // uint64_t
-
- break;
- case sizeof(uint32_t):
- case sizeof(uint16_t):
- case sizeof(uint8_t):
+ assert(pkt.result == Unknown);
+ assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
+
+
+ pkt.time += pioDelay;
+ pkt.allocate();
+ Addr daddr = (pkt.addr - pioAddr) >> 6;;
+ assert(pkt.size == sizeof(uint64_t));
+
+
+ DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
+
+ switch(daddr) {
+ case TSDEV_PC_WSBA0:
+ pkt.set(wsba[0]);
+ break;
+ case TSDEV_PC_WSBA1:
+ pkt.set(wsba[1]);
+ break;
+ case TSDEV_PC_WSBA2:
+ pkt.set(wsba[2]);
+ break;
+ case TSDEV_PC_WSBA3:
+ pkt.set(wsba[3]);
+ break;
+ case TSDEV_PC_WSM0:
+ pkt.set(wsm[0]);
+ break;
+ case TSDEV_PC_WSM1:
+ pkt.set(wsm[1]);
+ break;
+ case TSDEV_PC_WSM2:
+ pkt.set(wsm[2]);
+ break;
+ case TSDEV_PC_WSM3:
+ pkt.set(wsm[3]);
+ break;
+ case TSDEV_PC_TBA0:
+ pkt.set(tba[0]);
+ break;
+ case TSDEV_PC_TBA1:
+ pkt.set(tba[1]);
+ break;
+ case TSDEV_PC_TBA2:
+ pkt.set(tba[2]);
+ break;
+ case TSDEV_PC_TBA3:
+ pkt.set(tba[3]);
+ break;
+ case TSDEV_PC_PCTL:
+ pkt.set(pctl);
+ break;
+ case TSDEV_PC_PLAT:
+ panic("PC_PLAT not implemented\n");
+ case TSDEV_PC_RES:
+ panic("PC_RES not implemented\n");
+ case TSDEV_PC_PERROR:
+ pkt.set((uint64_t)0x00);
+ break;
+ case TSDEV_PC_PERRMASK:
+ pkt.set((uint64_t)0x00);
+ break;
+ case TSDEV_PC_PERRSET:
+ panic("PC_PERRSET not implemented\n");
+ case TSDEV_PC_TLBIV:
+ panic("PC_TLBIV not implemented\n");
+ case TSDEV_PC_TLBIA:
+ pkt.set((uint64_t)0x00); // shouldn't be readable, but linux
+ break;
+ case TSDEV_PC_PMONCTL:
+ panic("PC_PMONCTL not implemented\n");
+ case TSDEV_PC_PMONCNT:
+ panic("PC_PMONCTN not implemented\n");
default:
- panic("invalid access size(?) for tsunami register!\n\n");
+ panic("Default in PChip Read reached reading 0x%x\n", daddr);
}
- DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
+ pkt.result = Success;
+ return pioDelay;
- return NoFault;
}
-Fault
-TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
+Tick
+TsunamiPChip::write(Packet &pkt)
{
- DPRINTF(Tsunami, "write - va=%#x size=%d \n",
- req->vaddr, req->size);
-
- Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
-
- switch (req->size) {
-
- case sizeof(uint64_t):
- switch(daddr) {
- case TSDEV_PC_WSBA0:
- wsba[0] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_WSBA1:
- wsba[1] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_WSBA2:
- wsba[2] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_WSBA3:
- wsba[3] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_WSM0:
- wsm[0] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_WSM1:
- wsm[1] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_WSM2:
- wsm[2] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_WSM3:
- wsm[3] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_TBA0:
- tba[0] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_TBA1:
- tba[1] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_TBA2:
- tba[2] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_TBA3:
- tba[3] = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_PCTL:
- pctl = *(uint64_t*)data;
- return NoFault;
- case TSDEV_PC_PLAT:
- panic("PC_PLAT not implemented\n");
- case TSDEV_PC_RES:
- panic("PC_RES not implemented\n");
- case TSDEV_PC_PERROR:
- return NoFault;
- case TSDEV_PC_PERRMASK:
- panic("PC_PERRMASK not implemented\n");
- case TSDEV_PC_PERRSET:
- panic("PC_PERRSET not implemented\n");
- case TSDEV_PC_TLBIV:
- panic("PC_TLBIV not implemented\n");
- case TSDEV_PC_TLBIA:
- return NoFault; // value ignored, supposted to invalidate SG TLB
- case TSDEV_PC_PMONCTL:
- panic("PC_PMONCTL not implemented\n");
- case TSDEV_PC_PMONCNT:
- panic("PC_PMONCTN not implemented\n");
- default:
- panic("Default in PChip Read reached reading 0x%x\n", daddr);
-
- } // uint64_t
-
- break;
- case sizeof(uint32_t):
- case sizeof(uint16_t):
- case sizeof(uint8_t):
- default:
- panic("invalid access size(?) for tsunami register!\n\n");
- }
-
- DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
-
- return NoFault;
+ pkt.time += pioDelay;
+
+ assert(pkt.result == Unknown);
+ assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
+ Addr daddr = (pkt.addr - pioAddr) >> 6;
+
+ assert(pkt.size == sizeof(uint64_t));
+
+ DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
+
+ switch(daddr) {
+ case TSDEV_PC_WSBA0:
+ wsba[0] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_WSBA1:
+ wsba[1] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_WSBA2:
+ wsba[2] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_WSBA3:
+ wsba[3] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_WSM0:
+ wsm[0] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_WSM1:
+ wsm[1] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_WSM2:
+ wsm[2] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_WSM3:
+ wsm[3] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_TBA0:
+ tba[0] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_TBA1:
+ tba[1] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_TBA2:
+ tba[2] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_TBA3:
+ tba[3] = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_PCTL:
+ pctl = pkt.get<uint64_t>();
+ break;
+ case TSDEV_PC_PLAT:
+ panic("PC_PLAT not implemented\n");
+ case TSDEV_PC_RES:
+ panic("PC_RES not implemented\n");
+ case TSDEV_PC_PERROR:
+ break;
+ case TSDEV_PC_PERRMASK:
+ panic("PC_PERRMASK not implemented\n");
+ case TSDEV_PC_PERRSET:
+ panic("PC_PERRSET not implemented\n");
+ case TSDEV_PC_TLBIV:
+ panic("PC_TLBIV not implemented\n");
+ case TSDEV_PC_TLBIA:
+ break; // value ignored, supposted to invalidate SG TLB
+ case TSDEV_PC_PMONCTL:
+ panic("PC_PMONCTL not implemented\n");
+ case TSDEV_PC_PMONCNT:
+ panic("PC_PMONCTN not implemented\n");
+ default:
+ panic("Default in PChip write reached reading 0x%x\n", daddr);
+
+ } // uint64_t
+
+ pkt.result = Success;
+ return pioDelay;
}
#define DMA_ADDR_MASK ULL(0x3ffffffff)
@@ -311,10 +285,7 @@ TsunamiPChip::translatePciToDma(Addr busAddr)
baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
- memcpy((void *)&pteEntry,
- tsunami->system->
- physmem->dma_addr(pteAddr, sizeof(uint64_t)),
- sizeof(uint64_t));
+ pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
@@ -351,38 +322,37 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(tba, 4);
}
-Tick
-TsunamiPChip::cacheAccess(MemReqPtr &req)
-{
- return curTick + pioLatency;
-}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
- SimObjectParam<Tsunami *> tsunami;
- SimObjectParam<MemoryController *> mmu;
- Param<Addr> addr;
- SimObjectParam<Bus*> pio_bus;
+ Param<Addr> pio_addr;
Param<Tick> pio_latency;
- SimObjectParam<HierParams *> hier;
+ SimObjectParam<Platform *> platform;
+ SimObjectParam<System *> system;
+ SimObjectParam<Tsunami *> tsunami;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
- INIT_PARAM(tsunami, "Tsunami"),
- INIT_PARAM(mmu, "Memory Controller"),
- INIT_PARAM(addr, "Device Address"),
- INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
+ INIT_PARAM(pio_addr, "Device Address"),
+ INIT_PARAM(pio_latency, "Programmed IO latency"),
+ INIT_PARAM(platform, "platform"),
+ INIT_PARAM(system, "system object"),
+ INIT_PARAM(tsunami, "Tsunami")
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
{
- return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
- pio_bus, pio_latency);
+ TsunamiPChip::Params *p = new TsunamiPChip::Params;
+ p->name = getInstanceName();
+ p->pio_addr = pio_addr;
+ p->pio_delay = pio_latency;
+ p->platform = platform;
+ p->system = system;
+ p->tsunami = tsunami;
+ return new TsunamiPChip(p);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 23:16:19 +0000