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-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @file
- * Defines a 8250 UART
- */
-
-#ifndef __TSUNAMI_UART_HH__
-#define __TSUNAMI_UART_HH__
-
-#include "dev/tsunamireg.h"
-#include "base/range.hh"
-#include "dev/io_device.hh"
-#include "dev/uart.hh"
-
-
-/* UART8250 Interrupt ID Register
- * bit 0 Interrupt Pending 0 = true, 1 = false
- * bit 2:1 ID of highest priority interrupt
- * bit 7:3 zeroes
- */
-#define IIR_NOPEND 0x1
-
-// Interrupt IDs
-#define IIR_MODEM 0x00 /* Modem Status (lowest priority) */
-#define IIR_TXID 0x02 /* Tx Data */
-#define IIR_RXID 0x04 /* Rx Data */
-#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
-
-class SimConsole;
-class MemoryController;
-class Platform;
-
-class Uart8250 : public Uart
-{
-
-
- protected:
- uint8_t IER, DLAB, LCR, MCR;
-
- class IntrEvent : public Event
- {
- protected:
- Uart8250 *uart;
- int intrBit;
- public:
- IntrEvent(Uart8250 *u, int bit);
- virtual void process();
- virtual const char *description();
- void scheduleIntr();
- };
-
- IntrEvent txIntrEvent;
- IntrEvent rxIntrEvent;
-
- public:
- Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
- Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
- Platform *p);
-
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
-
-
- /**
- * Inform the uart that there is data available.
- */
- virtual void dataAvailable();
-
-
- /**
- * Return if we have an interrupt pending
- * @return interrupt status
- */
- virtual bool intStatus() { return status ? true : false; }
-
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-};
-
-#endif // __TSUNAMI_UART_HH__