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-rw-r--r--dev/etherpkt.hh12
-rw-r--r--dev/ide_ctrl.cc3
-rw-r--r--dev/ide_disk.cc14
-rw-r--r--dev/ns_gige.cc84
-rw-r--r--dev/ns_gige.hh18
-rw-r--r--dev/tsunami.hh5
6 files changed, 54 insertions, 82 deletions
diff --git a/dev/etherpkt.hh b/dev/etherpkt.hh
index 9c5f00491..1b6e9858f 100644
--- a/dev/etherpkt.hh
+++ b/dev/etherpkt.hh
@@ -38,7 +38,6 @@
#include <assert.h>
#include "base/refcnt.hh"
-#include "base/inet.hh"
#include "sim/host.hh"
/*
@@ -58,17 +57,6 @@ class PacketData : public RefCounted
~PacketData() { if (data) delete [] data; }
public:
- const EthHdr *eth() const { return (const EthHdr *)data; }
- const IpHdr *ip() const {const EthHdr *h = eth(); return h ? h->ip() : 0;}
- const TcpHdr *tcp() const {const IpHdr *h = ip(); return h ? h->tcp() : 0;}
- const UdpHdr *udp() const {const IpHdr *h = ip(); return h ? h->udp() : 0;}
-
- EthHdr *eth() { return (EthHdr *)data; }
- IpHdr *ip() { EthHdr *h = eth(); return h ? h->ip() : 0; }
- TcpHdr *tcp() { IpHdr *h = ip(); return h ? h->tcp() : 0; }
- UdpHdr *udp() { IpHdr *h = ip(); return h ? h->udp() : 0; }
-
- public:
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index dbec6d743..787049533 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -63,9 +63,6 @@ IdeController::IdeController(const string &name, IntrControl *ic,
Bus *host_bus, Tick pio_latency, HierParams *hier)
: PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
{
- // put back pointer into Tsunami
- tsunami->disk_controller = this;
-
// initialize the PIO interface addresses
pri_cmd_addr = 0;
pri_cmd_size = BARSize[0];
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index 99724f077..405b77eca 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -35,7 +35,6 @@
#include <deque>
#include <string>
-#include "arch/alpha/pmap.h"
#include "base/cprintf.hh" // csprintf
#include "base/trace.hh"
#include "dev/disk_image.hh"
@@ -51,6 +50,7 @@
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "sim/universe.hh"
+#include "targetarch/isa_traits.hh"
using namespace std;
@@ -188,14 +188,14 @@ IdeDisk::bytesInDmaPage(Addr curAddr, uint32_t bytesLeft)
uint32_t bytesInPage = 0;
// First calculate how many bytes could be in the page
- if (bytesLeft > ALPHA_PGBYTES)
- bytesInPage = ALPHA_PGBYTES;
+ if (bytesLeft > TheISA::PageBytes)
+ bytesInPage = TheISA::PageBytes;
else
bytesInPage = bytesLeft;
// Next, see if we have crossed a page boundary, and adjust
Addr upperBound = curAddr + bytesInPage;
- Addr pageBound = alpha_trunc_page(curAddr) + ALPHA_PGBYTES;
+ Addr pageBound = TheISA::TruncPage(curAddr) + TheISA::PageBytes;
assert(upperBound >= curAddr && "DMA read wraps around address space!\n");
@@ -510,7 +510,7 @@ IdeDisk::dmaWriteDone()
// setup the initial page and DMA address
curAddr = curPrd.getBaseAddr();
- pageAddr = alpha_trunc_page(curAddr);
+ pageAddr = TheISA::TruncPage(curAddr);
dmaAddr = pciToDma(curAddr);
// clear out the data buffer
@@ -518,14 +518,14 @@ IdeDisk::dmaWriteDone()
while (bytesRead < curPrd.getByteCount()) {
// see if we have crossed into a new page
- if (pageAddr != alpha_trunc_page(curAddr)) {
+ if (pageAddr != TheISA::TruncPage(curAddr)) {
// write the data to memory
memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
(void *)(dataBuffer + (bytesRead - bytesInPage)),
bytesInPage);
// update the DMA address and page address
- pageAddr = alpha_trunc_page(curAddr);
+ pageAddr = TheISA::TruncPage(curAddr);
dmaAddr = pciToDma(curAddr);
bytesInPage = 0;
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 8eb41e5cc..2b19cebe9 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -86,7 +86,7 @@ const char *NsDmaState[] =
};
using namespace std;
-
+using namespace Net;
///////////////////////////////////////////////////////////////////////
//
@@ -99,7 +99,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
- uint32_t func, bool rx_filter, const int eaddr[6],
+ uint32_t func, bool rx_filter, EthAddr eaddr,
uint32_t tx_fifo_size, uint32_t rx_fifo_size)
: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), ioEnable(false),
maxTxFifoSize(tx_fifo_size), maxRxFifoSize(rx_fifo_size),
@@ -119,8 +119,6 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
physmem(pmem), intctrl(i), intrTick(0), cpuPendingIntr(false),
intrEvent(0), interface(0)
{
- tsunami->ethernet = this;
-
if (header_bus) {
pioInterface = newPioInterface(name, hier, header_bus, this,
&NSGigE::cacheAccess);
@@ -151,12 +149,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
dmaWriteFactor = dma_write_factor;
regsReset();
- rom.perfectMatch[0] = eaddr[0];
- rom.perfectMatch[1] = eaddr[1];
- rom.perfectMatch[2] = eaddr[2];
- rom.perfectMatch[3] = eaddr[3];
- rom.perfectMatch[4] = eaddr[4];
- rom.perfectMatch[5] = eaddr[5];
+ memcpy(&rom.perfectMatch, eaddr.bytes(), ETH_ADDR_LEN);
}
NSGigE::~NSGigE()
@@ -1339,10 +1332,10 @@ NSGigE::rxKick()
#if TRACING_ON
if (DTRACE(Ethernet)) {
- const IpHdr *ip = rxPacket->ip();
+ IpPtr ip(rxPacket);
if (ip) {
DPRINTF(Ethernet, "ID is %d\n", ip->id());
- const TcpHdr *tcp = rxPacket->tcp();
+ TcpPtr tcp(ip);
if (tcp) {
DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
tcp->sport(), tcp->dport());
@@ -1401,36 +1394,38 @@ NSGigE::rxKick()
*/
if (rxFilterEnable) {
rxDescCache.cmdsts &= ~CMDSTS_DEST_MASK;
- EthHdr *eth = rxFifoFront()->eth();
- if (eth->unicast())
+ const EthAddr &dst = rxFifoFront()->dst();
+ if (dst->unicast())
rxDescCache.cmdsts |= CMDSTS_DEST_SELF;
- if (eth->multicast())
+ if (dst->multicast())
rxDescCache.cmdsts |= CMDSTS_DEST_MULTI;
- if (eth->broadcast())
+ if (dst->broadcast())
rxDescCache.cmdsts |= CMDSTS_DEST_MASK;
}
#endif
- if (extstsEnable && rxPacket->ip()) {
+ IpPtr ip(rxPacket);
+ if (extstsEnable && ip) {
rxDescCache.extsts |= EXTSTS_IPPKT;
rxIpChecksums++;
- IpHdr *ip = rxPacket->ip();
- if (ip->ip_cksum() != 0) {
+ if (cksum(ip) != 0) {
DPRINTF(EthernetCksum, "Rx IP Checksum Error\n");
rxDescCache.extsts |= EXTSTS_IPERR;
}
- if (rxPacket->tcp()) {
+ TcpPtr tcp(ip);
+ UdpPtr udp(ip);
+ if (tcp) {
rxDescCache.extsts |= EXTSTS_TCPPKT;
rxTcpChecksums++;
- if (ip->tu_cksum() != 0) {
+ if (cksum(tcp) != 0) {
DPRINTF(EthernetCksum, "Rx TCP Checksum Error\n");
rxDescCache.extsts |= EXTSTS_TCPERR;
}
- } else if (rxPacket->udp()) {
+ } else if (udp) {
rxDescCache.extsts |= EXTSTS_UDPPKT;
rxUdpChecksums++;
- if (ip->tu_cksum() != 0) {
+ if (cksum(udp) != 0) {
DPRINTF(EthernetCksum, "Rx UDP Checksum Error\n");
rxDescCache.extsts |= EXTSTS_UDPERR;
}
@@ -1548,10 +1543,10 @@ NSGigE::transmit()
if (interface->sendPacket(txFifo.front())) {
#if TRACING_ON
if (DTRACE(Ethernet)) {
- const IpHdr *ip = txFifo.front()->ip();
+ IpPtr ip(txFifo.front());
if (ip) {
DPRINTF(Ethernet, "ID is %d\n", ip->id());
- const TcpHdr *tcp = txFifo.front()->tcp();
+ TcpPtr tcp(ip);
if (tcp) {
DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
tcp->sport(), tcp->dport());
@@ -1814,21 +1809,21 @@ NSGigE::txKick()
DPRINTF(EthernetSM, "This packet is done, let's wrap it up\n");
/* deal with the the packet that just finished */
if ((regs.vtcr & VTCR_PPCHK) && extstsEnable) {
- IpHdr *ip = txPacket->ip();
+ IpPtr ip(txPacket);
if (txDescCache.extsts & EXTSTS_UDPPKT) {
- UdpHdr *udp = txPacket->udp();
+ UdpPtr udp(ip);
udp->sum(0);
- udp->sum(ip->tu_cksum());
+ udp->sum(cksum(udp));
txUdpChecksums++;
} else if (txDescCache.extsts & EXTSTS_TCPPKT) {
- TcpHdr *tcp = txPacket->tcp();
+ TcpPtr tcp(ip);
tcp->sum(0);
- tcp->sum(ip->tu_cksum());
+ tcp->sum(cksum(tcp));
txTcpChecksums++;
}
if (txDescCache.extsts & EXTSTS_IPPKT) {
ip->sum(0);
- ip->sum(ip->ip_cksum());
+ ip->sum(cksum(ip));
txIpChecksums++;
}
}
@@ -1987,31 +1982,31 @@ NSGigE::transferDone()
}
bool
-NSGigE::rxFilter(PacketPtr packet)
+NSGigE::rxFilter(PacketPtr &packet)
{
+ EthPtr eth = packet;
bool drop = true;
string type;
- EthHdr *eth = packet->eth();
- if (eth->unicast()) {
+ const EthAddr &dst = eth->dst();
+ if (dst.unicast()) {
// If we're accepting all unicast addresses
if (acceptUnicast)
drop = false;
// If we make a perfect match
- if (acceptPerfect &&
- memcmp(rom.perfectMatch, packet->data, EADDR_LEN) == 0)
+ if (acceptPerfect && dst == rom.perfectMatch)
drop = false;
if (acceptArp && eth->type() == ETH_TYPE_ARP)
drop = false;
- } else if (eth->broadcast()) {
+ } else if (dst.broadcast()) {
// if we're accepting broadcasts
if (acceptBroadcast)
drop = false;
- } else if (eth->multicast()) {
+ } else if (dst.multicast()) {
// if we're accepting all multicasts
if (acceptMulticast)
drop = false;
@@ -2027,7 +2022,7 @@ NSGigE::rxFilter(PacketPtr packet)
}
bool
-NSGigE::recvPacket(PacketPtr packet)
+NSGigE::recvPacket(PacketPtr &packet)
{
rxBytes += packet->length;
rxPackets++;
@@ -2120,7 +2115,7 @@ NSGigE::serialize(ostream &os)
SERIALIZE_SCALAR(regs.taner);
SERIALIZE_SCALAR(regs.tesr);
- SERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
+ SERIALIZE_ARRAY(rom.perfectMatch, ETH_ADDR_LEN);
SERIALIZE_SCALAR(ioEnable);
@@ -2277,7 +2272,7 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(regs.taner);
UNSERIALIZE_SCALAR(regs.tesr);
- UNSERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
+ UNSERIALIZE_ARRAY(rom.perfectMatch, ETH_ADDR_LEN);
UNSERIALIZE_SCALAR(ioEnable);
@@ -2517,16 +2512,13 @@ END_INIT_SIM_OBJECT_PARAMS(NSGigE)
CREATE_SIM_OBJECT(NSGigE)
{
- int eaddr[6];
- sscanf(((string)hardware_address).c_str(), "%x:%x:%x:%x:%x:%x",
- &eaddr[0], &eaddr[1], &eaddr[2], &eaddr[3], &eaddr[4], &eaddr[5]);
-
return new NSGigE(getInstanceName(), intr_ctrl, intr_delay,
physmem, tx_delay, rx_delay, mmu, hier, header_bus,
payload_bus, pio_latency, dma_desc_free, dma_data_free,
dma_read_delay, dma_write_delay, dma_read_factor,
dma_write_factor, configspace, configdata,
- tsunami, pci_bus, pci_dev, pci_func, rx_filter, eaddr,
+ tsunami, pci_bus, pci_dev, pci_func, rx_filter,
+ EthAddr((string)hardware_address),
tx_fifo_size, rx_fifo_size);
}
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index b7838cf6f..60dcf3fc2 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -31,9 +31,10 @@
* DP83820 ethernet controller
*/
-#ifndef __NS_GIGE_HH__
-#define __NS_GIGE_HH__
+#ifndef __DEV_NS_GIGE_HH__
+#define __DEV_NS_GIGE_HH__
+#include "base/inet.hh"
#include "base/statistics.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
@@ -44,9 +45,6 @@
#include "mem/bus/bus.hh"
#include "sim/eventq.hh"
-/** length of ethernet address in bytes */
-#define EADDR_LEN 6
-
/**
* Ethernet device registers
*/
@@ -90,7 +88,7 @@ struct dp_rom {
* for perfect match memory.
* the linux driver doesn't use any other ROM
*/
- uint8_t perfectMatch[EADDR_LEN];
+ uint8_t perfectMatch[ETH_ADDR_LEN];
};
class IntrControl;
@@ -302,7 +300,7 @@ class NSGigE : public PciDev
* receive address filter
*/
bool rxFilterEnable;
- bool rxFilter(PacketPtr packet);
+ bool rxFilter(PacketPtr &packet);
bool acceptBroadcast;
bool acceptMulticast;
bool acceptUnicast;
@@ -339,7 +337,7 @@ class NSGigE : public PciDev
bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
- uint32_t func, bool rx_filter, const int eaddr[6],
+ uint32_t func, bool rx_filter, Net::EthAddr eaddr,
uint32_t tx_fifo_size, uint32_t rx_fifo_size);
~NSGigE();
@@ -352,7 +350,7 @@ class NSGigE : public PciDev
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
- bool recvPacket(PacketPtr packet);
+ bool recvPacket(PacketPtr &packet);
void transferDone();
void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
@@ -403,4 +401,4 @@ class NSGigEInt : public EtherInt
virtual void sendDone() { dev->transferDone(); }
};
-#endif // __NS_GIGE_HH__
+#endif // __DEV_NS_GIGE_HH__
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index db266d62d..4367383ff 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -62,12 +62,9 @@ class Tsunami : public Platform
/** Pointer to the system */
System *system;
+
/** Pointer to the TsunamiIO device which has the RTC */
TsunamiIO *io;
- /** Pointer to the disk controller device */
- IdeController *disk_controller;
- /** Pointer to the ethernet controller device */
- NSGigE *ethernet;
/** Pointer to the Tsunami CChip.
* The chip contains some configuration information and
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-21 06:48:36 +0000