diff options
Diffstat (limited to 'dev')
| -rw-r--r-- | dev/ide_disk.cc | 3 | ||||
| -rw-r--r-- | dev/ns_gige.hh | 2 | ||||
| -rw-r--r-- | dev/pcidev.cc | 10 | ||||
| -rw-r--r-- | dev/tsunami_io.cc | 127 | ||||
| -rw-r--r-- | dev/tsunami_io.hh | 25 | ||||
| -rw-r--r-- | dev/tsunamireg.h | 12 |
6 files changed, 170 insertions, 9 deletions
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc index 23d04bb5e..ae394c69e 100644 --- a/dev/ide_disk.cc +++ b/dev/ide_disk.cc @@ -134,6 +134,8 @@ IdeDisk::reset(int id) memset(&cmdReg, 0, sizeof(CommandReg_t)); memset(&curPrd.entry, 0, sizeof(PrdEntry_t)); + cmdReg.error = 1; + dmaInterfaceBytes = 0; curPrdAddr = 0; curSector = 0; @@ -745,6 +747,7 @@ IdeDisk::intrPost() // talk to controller to set interrupt if (ctrl) + ctrl->bmi_regs[BMIS0] |= IDEINTS; ctrl->intrPost(); } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index f39731493..9007ea6cf 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -99,7 +99,7 @@ class Bus; class PciConfigAll; /** - * NS DP82830 Ethernet device model + * NS DP83820 Ethernet device model */ class NSGigE : public PciDev { diff --git a/dev/pcidev.cc b/dev/pcidev.cc index f2bce33ca..93200a8c7 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -138,7 +138,13 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) case PCI_LATENCY_TIMER: *(uint8_t *)&config.data[offset] = htoa(byte_value); break; - + /* Do nothing for these read-only registers */ + case PCI0_INTERRUPT_PIN: + case PCI0_MINIMUM_GRANT: + case PCI0_MAXIMUM_LATENCY: + case PCI_CLASS_CODE: + case PCI_REVISION_ID: + break; default: panic("writing to a read only register"); } @@ -192,7 +198,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) htoa((word_value & ~0x3) | (htoa(config.data[offset]) & 0x3)); - if (word_value & ~0x1) { + if (word_value != 0x1) { Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO; Addr base_size = BARSize[barnum]; diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index da1062237..963bdc321 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -52,6 +52,8 @@ using namespace std; #define UNIX_YEAR_OFFSET 52 +struct tm TsunamiIO::tm = { 0 }; + // Timer Event for Periodic interrupt of RTC TsunamiIO::RTCEvent::RTCEvent(Tsunami* t, Tick i) : Event(&mainEventQueue), tsunami(t), interval(i) @@ -63,10 +65,16 @@ TsunamiIO::RTCEvent::RTCEvent(Tsunami* t, Tick i) void TsunamiIO::RTCEvent::process() { + static int intr_count = 0; DPRINTF(MC146818, "RTC Timer Interrupt\n"); schedule(curTick + interval); //Actually interrupt the processor here tsunami->cchip->postRTC(); + if (intr_count == 1023) + tm.tm_sec = (tm.tm_sec + 1) % 60; + + intr_count = (intr_count + 1) % 1024; + } const char * @@ -104,6 +112,11 @@ TsunamiIO::ClockEvent::ClockEvent() DPRINTF(Tsunami, "Clock Event Initilizing\n"); mode = 0; + + current_count.whole = 0; + latched_count.whole = 0; + latch_on = false; + read_msb = false; } void @@ -114,6 +127,8 @@ TsunamiIO::ClockEvent::process() status = 0x20; // set bit that linux is looking for else schedule(curTick + interval); + + current_count.whole--; //decrement count } void @@ -122,6 +137,8 @@ TsunamiIO::ClockEvent::Program(int count) DPRINTF(Tsunami, "Timer set to curTick + %d\n", count * interval); schedule(curTick + count * interval); status = 0; + + current_count.whole = count; } const char * @@ -143,6 +160,38 @@ TsunamiIO::ClockEvent::Status() } void +TsunamiIO::ClockEvent::LatchCount() +{ + if(!latch_on) { + latch_on = true; + read_msb = false; + latched_count.whole = current_count.whole; + } +} + +uint8_t +TsunamiIO::ClockEvent::Read() +{ + if(latch_on) { + if(!read_msb) { + read_msb = true; + return latched_count.half.lsb; + } else { + latch_on = false; + return latched_count.half.msb; + } + } else { + if(!read_msb) { + read_msb = true; + return current_count.half.lsb; + } else { + return current_count.half.msb; + } + } +} + + +void TsunamiIO::ClockEvent::serialize(std::ostream &os) { Tick time = scheduled() ? when() : 0; @@ -207,12 +256,19 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", req->vaddr, req->size, req->vaddr & 0xfff); - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20; switch(req->size) { case sizeof(uint8_t): switch(daddr) { + // PIC1 mask read + case TSDEV_PIC1_MASK: + *(uint8_t*)data = ~mask1; + return No_Fault; + case TSDEV_PIC2_MASK: + *(uint8_t*)data = ~mask2; + return No_Fault; case TSDEV_PIC1_ISR: // !!! If this is modified 64bit case needs to be too // Pal code has to do a 64 bit physical read because there is @@ -226,6 +282,9 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) case TSDEV_TMR_CTL: *(uint8_t*)data = timer2.Status(); return No_Fault; + case TSDEV_TMR0_DATA: + *(uint8_t *)data = timer0.Read(); + return No_Fault; case TSDEV_RTC_DATA: switch(RTCAddress) { case RTC_CNTRL_REGA: @@ -257,6 +316,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) return No_Fault; case RTC_DOM: *(uint8_t *)data = tm.tm_mday; + return No_Fault; case RTC_MON: *(uint8_t *)data = tm.tm_mon + 1; return No_Fault; @@ -267,6 +327,14 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) panic("Unknown RTC Address\n"); } + /* Added for keyboard reads */ + case TSDEV_KBD: + *(uint8_t *)data = 0x00; + return No_Fault; + /* Added for ATA PCI DMA */ + case ATA_PCI_DMA: + *(uint8_t *)data = 0x00; + return No_Fault; default: panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); } @@ -309,7 +377,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", req->vaddr, req->size, req->vaddr & 0xfff, dt64); - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20; switch(req->size) { case sizeof(uint8_t): @@ -355,8 +423,24 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data) case TSDEV_TMR_CTL: return No_Fault; case TSDEV_TMR2_CTL: - if ((*(uint8_t*)data & 0x30) != 0x30) - panic("Only L/M write supported\n"); + switch((*(uint8_t*)data >> 4) & 0x3) { + case 0x0: + switch(*(uint8_t*)data >> 6) { + case 0: + timer0.LatchCount(); + break; + case 2: + timer2.LatchCount(); + break; + default: + panic("Read Back Command not implemented\n"); + } + break; + case 0x3: + break; + default: + panic("Only L/M write and Counter-Latch read supported\n"); + } switch(*(uint8_t*)data >> 6) { case 0: @@ -396,8 +480,41 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data) case TSDEV_RTC_ADDR: RTCAddress = *(uint8_t*)data; return No_Fault; + case TSDEV_KBD: + return No_Fault; case TSDEV_RTC_DATA: - panic("RTC Write not implmented (rtc.o won't work)\n"); + switch(RTCAddress) { + case RTC_CNTRL_REGA: + return No_Fault; + case RTC_CNTRL_REGB: + return No_Fault; + case RTC_CNTRL_REGC: + return No_Fault; + case RTC_CNTRL_REGD: + return No_Fault; + case RTC_SEC: + tm.tm_sec = *(uint8_t *)data; + return No_Fault; + case RTC_MIN: + tm.tm_min = *(uint8_t *)data; + return No_Fault; + case RTC_HR: + tm.tm_hour = *(uint8_t *)data; + return No_Fault; + case RTC_DOW: + tm.tm_wday = *(uint8_t *)data; + return No_Fault; + case RTC_DOM: + tm.tm_mday = *(uint8_t *)data; + return No_Fault; + case RTC_MON: + tm.tm_mon = *(uint8_t *)data - 1; + return No_Fault; + case RTC_YEAR: + tm.tm_year = *(uint8_t *)data + UNIX_YEAR_OFFSET; + return No_Fault; + //panic("RTC Write not implmented (rtc.o won't work)\n"); + } default: panic("I/O Write - va%#x size %d\n", req->vaddr, req->size); } diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index d5d106db3..dca651d4b 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -51,7 +51,7 @@ class TsunamiIO : public PioDevice /** The size of mappad from the above address */ static const Addr size = 0xff; - struct tm tm; + static struct tm tm; /** * In Tsunami RTC only has two i/o ports one for data and one for @@ -75,6 +75,18 @@ class TsunamiIO : public PioDevice uint8_t mode; /** The status of the PIT */ uint8_t status; + /** The counts (current and latched) of the PIT */ + union { + uint16_t whole; + struct { + uint8_t msb; + uint8_t lsb; + } half; + } current_count, latched_count; + + /** Thse state of the output latch of the PIT */ + bool latch_on; + bool read_msb; public: /** @@ -111,6 +123,17 @@ class TsunamiIO : public PioDevice uint8_t Status(); /** + * Latch the count of the PIT. + */ + void LatchCount(); + + /** + * The current PIT count. + * @return the count of the PIT + */ + uint8_t Read(); + + /** * Serialize this object to the given output stream. * @param os The stream to serialize to. */ diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 5fbfd5c31..8b290deb1 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -123,6 +123,18 @@ #define TSDEV_TMR2_DATA 0x42 #define TSDEV_TMR0_DATA 0x40 +/* Added for keyboard accesses */ +#define TSDEV_KBD 0x64 + +/* Added for ATA PCI DMA */ +#define ATA_PCI_DMA 0x00 +#define ATA_PCI_DMA2 0x02 +#define ATA_PCI_DMA3 0x16 +#define ATA_PCI_DMA4 0x17 +#define ATA_PCI_DMA5 0x1a +#define ATA_PCI_DMA6 0x11 +#define ATA_PCI_DMA7 0x14 + #define TSDEV_RTC_ADDR 0x70 #define TSDEV_RTC_DATA 0x71 |