diff options
Diffstat (limited to 'dev')
-rw-r--r-- | dev/alpha_console.cc | 4 | ||||
-rw-r--r-- | dev/ide_ctrl.cc | 20 | ||||
-rw-r--r-- | dev/ns_gige.cc | 4 | ||||
-rw-r--r-- | dev/pciconfigall.cc | 4 | ||||
-rw-r--r-- | dev/tsunami_cchip.cc | 4 | ||||
-rw-r--r-- | dev/tsunami_io.cc | 4 | ||||
-rw-r--r-- | dev/tsunami_pchip.cc | 4 | ||||
-rw-r--r-- | dev/uart.cc | 5 |
8 files changed, 24 insertions, 25 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 964ab442c..7deabe2fc 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -98,7 +98,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) { memset(data, 0, req->size); - Addr daddr = req->paddr - (addr & PA_IMPL_MASK); + Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); switch (req->size) { @@ -198,7 +198,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) return Machine_Check_Fault; } - Addr daddr = req->paddr - (addr & PA_IMPL_MASK); + Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); ExecContext *other_xc; switch (daddr) { diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index d08e61fbf..aa0217745 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -34,16 +34,16 @@ #include "base/trace.hh" #include "cpu/intr_control.hh" #include "dev/dma.hh" -#include "dev/pcireg.h" -#include "dev/pciconfigall.hh" -#include "dev/ide_disk.hh" #include "dev/ide_ctrl.hh" +#include "dev/ide_disk.hh" +#include "dev/pciconfigall.hh" +#include "dev/pcireg.h" +#include "dev/platform.hh" #include "dev/tsunami_cchip.hh" #include "mem/bus/bus.hh" +#include "mem/bus/dma_interface.hh" #include "mem/bus/pio_interface.hh" #include "mem/bus/pio_interface_impl.hh" -#include "mem/bus/dma_interface.hh" -#include "dev/tsunami.hh" #include "mem/functional_mem/memory_control.hh" #include "mem/functional_mem/physical_memory.hh" #include "sim/builder.hh" @@ -377,7 +377,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size)); - pri_cmd_addr &= PA_UNCACHED_MASK; + pri_cmd_addr &= EV5::PAddrUncachedMask; } break; @@ -388,7 +388,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size)); - pri_ctrl_addr &= PA_UNCACHED_MASK; + pri_ctrl_addr &= EV5::PAddrUncachedMask; } break; @@ -399,7 +399,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size)); - sec_cmd_addr &= PA_UNCACHED_MASK; + sec_cmd_addr &= EV5::PAddrUncachedMask; } break; @@ -410,7 +410,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size)); - sec_ctrl_addr &= PA_UNCACHED_MASK; + sec_ctrl_addr &= EV5::PAddrUncachedMask; } break; @@ -420,7 +420,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) if (pioInterface) pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size)); - bmi_addr &= PA_UNCACHED_MASK; + bmi_addr &= EV5::PAddrUncachedMask; } break; } diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 4d0b93ab9..8eca91510 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -339,7 +339,7 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data) if (pioInterface) pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0])); - BARAddrs[0] &= PA_UNCACHED_MASK; + BARAddrs[0] &= EV5::PAddrUncachedMask; } break; case PCI0_BASE_ADDR1: @@ -347,7 +347,7 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data) if (pioInterface) pioInterface->addAddrRange(RangeSize(BARAddrs[1], BARSize[1])); - BARAddrs[1] &= PA_UNCACHED_MASK; + BARAddrs[1] &= EV5::PAddrUncachedMask; } break; } diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 6fee30c10..d5302d9ad 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -71,7 +71,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) DPRINTF(PciConfigAll, "read va=%#x size=%d\n", req->vaddr, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; @@ -115,7 +115,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) Fault PciConfigAll::write(MemReqPtr &req, const uint8_t *data) { - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 20b39f21f..c389063d0 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -83,7 +83,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; ExecContext *xc = req->xc; switch (req->size) { @@ -169,7 +169,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n", req->vaddr, *(uint64_t*)data, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; bool supportedWrite = false; uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index fab1b4b38..51ff8b81c 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -196,7 +196,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", req->vaddr, req->size, req->vaddr & 0xfff); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); switch(req->size) { @@ -298,7 +298,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", req->vaddr, req->size, req->vaddr & 0xfff, dt64); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); switch(req->size) { case sizeof(uint8_t): diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index 4c94d12af..9af19d930 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -82,7 +82,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; switch (req->size) { @@ -171,7 +171,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "write - va=%#x size=%d \n", req->vaddr, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; switch (req->size) { diff --git a/dev/uart.cc b/dev/uart.cc index b71ab2d44..2ff94dda5 100644 --- a/dev/uart.cc +++ b/dev/uart.cc @@ -44,7 +44,6 @@ #include "mem/bus/pio_interface_impl.hh" #include "mem/functional_mem/memory_control.hh" #include "sim/builder.hh" -#include "targetarch/ev5.hh" using namespace std; @@ -118,7 +117,7 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a, Fault Uart::read(MemReqPtr &req, uint8_t *data) { - Addr daddr = req->paddr - (addr & PA_IMPL_MASK); + Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); DPRINTF(Uart, " read register %#x\n", daddr); @@ -246,7 +245,7 @@ Uart::read(MemReqPtr &req, uint8_t *data) Fault Uart::write(MemReqPtr &req, const uint8_t *data) { - Addr daddr = req->paddr - (addr & PA_IMPL_MASK); + Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data); |