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Diffstat (limited to 'dev')
-rw-r--r--dev/alpha_console.cc4
-rw-r--r--dev/ns_gige.cc9
-rw-r--r--dev/ns_gige.hh1
-rw-r--r--dev/ns_gige_reg.h1
-rw-r--r--dev/pcidev.hh6
-rw-r--r--dev/pktfifo.cc34
-rw-r--r--dev/pktfifo.hh29
-rw-r--r--dev/sinic.cc46
-rw-r--r--dev/sinic.hh2
-rw-r--r--dev/sinicreg.hh1
10 files changed, 98 insertions, 35 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 94f834b4f..6ca5e3a06 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
}
break;
default:
- return MachineCheckFault;
+ return genMachineCheckFault();
}
return NoFault;
@@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
val = *(uint64_t *)data;
break;
default:
- return MachineCheckFault;
+ return genMachineCheckFault();
}
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 4b08d8497..ed8c794f9 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -49,7 +49,7 @@
#include "sim/debug.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
const char *NsRxStateStrings[] =
{
@@ -767,6 +767,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
reg |= M5REG_RX_THREAD;
if (params()->tx_thread)
reg |= M5REG_TX_THREAD;
+ if (params()->rss)
+ reg |= M5REG_RSS;
break;
default:
@@ -3009,6 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
+ Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
@@ -3048,7 +3051,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
- INIT_PARAM(tx_thread, "")
+ INIT_PARAM(tx_thread, ""),
+ INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(NSGigE)
@@ -3093,6 +3097,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
+ params->rss = rss;
return new NSGigE(params);
}
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index cdd8e4b9e..59c55056e 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -385,6 +385,7 @@ class NSGigE : public PciDev
uint32_t rx_fifo_size;
bool rx_thread;
bool tx_thread;
+ bool rss;
bool dma_no_allocate;
};
diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h
index eadc60d03..5f6fa2cc5 100644
--- a/dev/ns_gige_reg.h
+++ b/dev/ns_gige_reg.h
@@ -306,6 +306,7 @@
/* M5 control register */
#define M5REG_RESERVED 0xfffffffc
+#define M5REG_RSS 0x00000004
#define M5REG_RX_THREAD 0x00000002
#define M5REG_TX_THREAD 0x00000001
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index 9427463bf..bdfc6b932 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -260,6 +260,7 @@ class PciDev : public DmaDevice
inline Fault
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
+ using namespace TheISA;
if (isBAR(req->paddr, 0))
return readBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
@@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return readBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return readBar5(req, req->paddr - BARAddrs[5], data);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
inline Fault
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
+ using namespace TheISA;
if (isBAR(req->paddr, 0))
return writeBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
@@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
return writeBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return writeBar5(req, req->paddr - BARAddrs[5], data);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
#endif // __DEV_PCIDEV_HH__
diff --git a/dev/pktfifo.cc b/dev/pktfifo.cc
index b4fab2d6f..639009be9 100644
--- a/dev/pktfifo.cc
+++ b/dev/pktfifo.cc
@@ -31,6 +31,36 @@
using namespace std;
+bool
+PacketFifo::copyout(void *dest, int offset, int len)
+{
+ char *data = (char *)dest;
+ if (offset + len >= size())
+ return false;
+
+ list<PacketPtr>::iterator p = fifo.begin();
+ list<PacketPtr>::iterator end = fifo.end();
+ while (len > 0) {
+ while (offset >= (*p)->length) {
+ offset -= (*p)->length;
+ ++p;
+ }
+
+ if (p == end)
+ panic("invalid fifo");
+
+ int size = min((*p)->length - offset, len);
+ memcpy(data, (*p)->data, size);
+ offset = 0;
+ len -= size;
+ data += size;
+ ++p;
+ }
+
+ return true;
+}
+
+
void
PacketFifo::serialize(const string &base, ostream &os)
{
@@ -40,8 +70,8 @@ PacketFifo::serialize(const string &base, ostream &os)
paramOut(os, base + ".packets", fifo.size());
int i = 0;
- std::list<PacketPtr>::iterator p = fifo.begin();
- std::list<PacketPtr>::iterator end = fifo.end();
+ list<PacketPtr>::iterator p = fifo.begin();
+ list<PacketPtr>::iterator end = fifo.end();
while (p != end) {
(*p)->serialize(csprintf("%s.packet%d", base, i), os);
++p;
diff --git a/dev/pktfifo.hh b/dev/pktfifo.hh
index e63fd291f..e245840a8 100644
--- a/dev/pktfifo.hh
+++ b/dev/pktfifo.hh
@@ -127,6 +127,35 @@ class PacketFifo
fifo.erase(i);
}
+ bool copyout(void *dest, int offset, int len);
+
+ int countPacketsBefore(iterator end)
+ {
+ iterator i = fifo.begin();
+ int count = 0;
+
+ while (i != end) {
+ ++count;
+ ++i;
+ }
+
+ return count;
+ }
+
+ int countPacketsAfter(iterator i)
+ {
+ iterator end = fifo.end();
+ int count = 0;
+
+ while (i != end) {
+ ++count;
+ ++i;
+ }
+
+ return count;
+ }
+
+
/**
* Serialization stuff
*/
diff --git a/dev/sinic.cc b/dev/sinic.cc
index c499d2f49..363994919 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -47,7 +47,7 @@
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
using namespace Net;
using namespace TheISA;
@@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
- if (fault == MachineCheckFault) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;
@@ -376,7 +376,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
Fault
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
+ int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
@@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
- if (fault == MachineCheckFault) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;
@@ -472,7 +472,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
Fault
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
+ int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
@@ -489,30 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
- //uint32_t reg32 = *(uint32_t *)data;
+ uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
+ VirtualReg &vnic = virtualRegs[index];
+
DPRINTF(EthernetPIO,
"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
- info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr,
- req->paddr, req->vaddr, req->size);
+ info.name, cpu, info.size == 4 ? reg32 : reg64,
+ daddr, req->paddr, req->vaddr, req->size);
prepareWrite(cpu, index);
- regWrite(daddr, cpu, data);
-
- return NoFault;
-}
-
-void
-Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
-{
- Addr index = daddr >> Regs::VirtualShift;
- Addr raddr = daddr & Regs::VirtualMask;
-
- uint32_t reg32 = *(uint32_t *)data;
- uint64_t reg64 = *(uint64_t *)data;
- VirtualReg &vnic = virtualRegs[index];
-
switch (raddr) {
case Regs::Config:
changeConfig(reg32);
@@ -559,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
}
break;
}
+
+ return NoFault;
}
void
@@ -772,6 +761,8 @@ Device::reset()
regs.Config |= Config_RxThread;
if (params()->tx_thread)
regs.Config |= Config_TxThread;
+ if (params()->rss)
+ regs.Config |= Config_RSS;
regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
regs.RxMaxCopy = params()->rx_max_copy;
regs.TxMaxCopy = params()->tx_max_copy;
@@ -1635,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
+ Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(Device)
@@ -1677,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
- INIT_PARAM(tx_thread, "")
+ INIT_PARAM(tx_thread, ""),
+ INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(Device)
@@ -1725,6 +1718,7 @@ CREATE_SIM_OBJECT(Device)
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
+ params->rss = rss;
return new Device(params);
}
diff --git a/dev/sinic.hh b/dev/sinic.hh
index 97ebf4c30..25172fa45 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -280,7 +280,6 @@ class Device : public Base
Fault iprRead(Addr daddr, int cpu, uint64_t &result);
Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
- void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
/**
@@ -356,6 +355,7 @@ class Device : public Base
bool dma_no_allocate;
bool rx_thread;
bool tx_thread;
+ bool rss;
};
protected:
diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh
index fc1f4c06b..f90432398 100644
--- a/dev/sinicreg.hh
+++ b/dev/sinicreg.hh
@@ -81,6 +81,7 @@ __SINIC_REG32(HwAddr, 0x60); // 64: mac address
__SINIC_REG32(Size, 0x68); // register addres space size
// Config register bits
+__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling
__SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads
__SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread
__SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 09:39:44 +0000