diff options
Diffstat (limited to 'dev')
| -rw-r--r-- | dev/alpha_access.h | 6 | ||||
| -rw-r--r-- | dev/alpha_console.cc | 51 | ||||
| -rw-r--r-- | dev/alpha_console.hh | 6 | ||||
| -rw-r--r-- | dev/baddev.cc | 5 | ||||
| -rw-r--r-- | dev/baddev.hh | 4 | ||||
| -rw-r--r-- | dev/ide_ctrl.cc | 5 | ||||
| -rw-r--r-- | dev/ide_ctrl.hh | 4 | ||||
| -rw-r--r-- | dev/ide_disk.cc | 1 | ||||
| -rw-r--r-- | dev/isa_fake.cc | 5 | ||||
| -rw-r--r-- | dev/isa_fake.hh | 4 | ||||
| -rw-r--r-- | dev/ns_gige.cc | 66 | ||||
| -rw-r--r-- | dev/ns_gige.hh | 14 | ||||
| -rw-r--r-- | dev/pciconfigall.cc | 5 | ||||
| -rw-r--r-- | dev/pciconfigall.hh | 4 | ||||
| -rw-r--r-- | dev/pcidev.cc | 28 | ||||
| -rw-r--r-- | dev/pcidev.hh | 36 | ||||
| -rw-r--r-- | dev/platform.cc | 1 | ||||
| -rw-r--r-- | dev/simple_disk.hh | 20 | ||||
| -rw-r--r-- | dev/sinic.cc | 54 | ||||
| -rw-r--r-- | dev/sinic.hh | 22 | ||||
| -rw-r--r-- | dev/sinicreg.hh | 40 | ||||
| -rw-r--r-- | dev/tsunami.cc | 2 | ||||
| -rw-r--r-- | dev/tsunami_cchip.cc | 6 | ||||
| -rw-r--r-- | dev/tsunami_cchip.hh | 4 | ||||
| -rw-r--r-- | dev/tsunami_io.cc | 6 | ||||
| -rw-r--r-- | dev/tsunami_io.hh | 4 | ||||
| -rw-r--r-- | dev/tsunami_pchip.cc | 6 | ||||
| -rw-r--r-- | dev/tsunami_pchip.hh | 4 | ||||
| -rw-r--r-- | dev/uart.hh | 4 | ||||
| -rw-r--r-- | dev/uart8250.cc | 5 | ||||
| -rw-r--r-- | dev/uart8250.hh | 4 |
31 files changed, 165 insertions, 261 deletions
diff --git a/dev/alpha_access.h b/dev/alpha_access.h index a20a05535..5a1df6f39 100644 --- a/dev/alpha_access.h +++ b/dev/alpha_access.h @@ -33,7 +33,7 @@ * System Console Memory Mapped Register Definition */ -#define ALPHA_ACCESS_VERSION (1303) +#define ALPHA_ACCESS_VERSION (1305) #ifdef CONSOLE typedef unsigned uint32_t; @@ -67,9 +67,7 @@ struct AlphaAccess uint64_t inputChar; // 68: Placeholder for input // MP boot - uint64_t bootStrapImpure; // 70: - uint32_t bootStrapCPU; // 78: - uint32_t align2; // 7C: Dummy placeholder for alignment + uint64_t cpuStack[64]; // 70: }; #endif // __ALPHA_ACCESS_H__ diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 38fbbdef0..2e8bbd1dd 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -53,6 +53,7 @@ #include "sim/system.hh" using namespace std; +using namespace AlphaISA; AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, System *s, BaseCPU *c, Platform *p, @@ -80,9 +81,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, alphaAccess->diskOperation = 0; alphaAccess->outputChar = 0; alphaAccess->inputChar = 0; - alphaAccess->bootStrapImpure = 0; - alphaAccess->bootStrapCPU = 0; - alphaAccess->align2 = 0; + bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack)); system->setAlphaAccess(addr); } @@ -99,7 +98,7 @@ AlphaConsole::startup() alphaAccess->intrClockFrequency = platform->intrFrequency(); } -Fault * +Fault AlphaConsole::read(MemReqPtr &req, uint8_t *data) { memset(data, 0, req->size); @@ -122,9 +121,6 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) case offsetof(AlphaAccess, numCPUs): *(uint32_t*)data = alphaAccess->numCPUs; break; - case offsetof(AlphaAccess, bootStrapCPU): - *(uint32_t*)data = alphaAccess->bootStrapCPU; - break; case offsetof(AlphaAccess, intrClockFrequency): *(uint32_t*)data = alphaAccess->intrClockFrequency; break; @@ -175,11 +171,14 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) case offsetof(AlphaAccess, outputChar): *(uint64_t*)data = alphaAccess->outputChar; break; - case offsetof(AlphaAccess, bootStrapImpure): - *(uint64_t*)data = alphaAccess->bootStrapImpure; - break; default: - panic("Unknown 64bit access, %#x\n", daddr); + int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / + sizeof(alphaAccess->cpuStack[0]); + + if (cpunum >= 0 && cpunum < 64) + *(uint64_t*)data = alphaAccess->cpuStack[cpunum]; + else + panic("Unknown 64bit access, %#x\n", daddr); } break; default: @@ -189,7 +188,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault AlphaConsole::write(MemReqPtr &req, const uint8_t *data) { uint64_t val; @@ -239,24 +238,18 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) console->out((char)(val & 0xff)); break; - case offsetof(AlphaAccess, bootStrapImpure): - alphaAccess->bootStrapImpure = val; - break; - - case offsetof(AlphaAccess, bootStrapCPU): - warn("%d: Trying to launch another CPU!", curTick); - assert(val > 0 && "Must not access primary cpu"); - - other_xc = req->xc->system->execContexts[val]; - other_xc->regs.intRegFile[16] = val; - other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val; - other_xc->regs.intRegFile[0] = val; - other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure; other_xc->activate(); //Start the cpu break; default: - return MachineCheckFault; + int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / + sizeof(alphaAccess->cpuStack[0]); + warn("%d: Trying to launch CPU number %d!", curTick, cpunum); + assert(val > 0 && "Must not access primary cpu"); + if (cpunum >= 0 && cpunum < 64) + alphaAccess->cpuStack[cpunum] = val; + else + panic("Unknown 64bit access, %#x\n", daddr); } return NoFault; @@ -287,8 +280,7 @@ AlphaConsole::Access::serialize(ostream &os) SERIALIZE_SCALAR(diskOperation); SERIALIZE_SCALAR(outputChar); SERIALIZE_SCALAR(inputChar); - SERIALIZE_SCALAR(bootStrapImpure); - SERIALIZE_SCALAR(bootStrapCPU); + SERIALIZE_ARRAY(cpuStack,64); } void @@ -310,8 +302,7 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(diskOperation); UNSERIALIZE_SCALAR(outputChar); UNSERIALIZE_SCALAR(inputChar); - UNSERIALIZE_SCALAR(bootStrapImpure); - UNSERIALIZE_SCALAR(bootStrapCPU); + UNSERIALIZE_ARRAY(cpuStack, 64); } void diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 75f0a3a67..2d1c1e634 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -96,7 +96,7 @@ class AlphaConsole : public PioDevice BaseCPU *cpu; Addr addr; - static const Addr size = 0x80; // equal to sizeof(alpha_access); + static const Addr size = sizeof(struct AlphaAccess); public: /** Standard Constructor */ @@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice /** * memory mapped reads and writes */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * standard serialization routines for checkpointing diff --git a/dev/baddev.cc b/dev/baddev.cc index b6ca919e4..87d683a5d 100644 --- a/dev/baddev.cc +++ b/dev/baddev.cc @@ -46,6 +46,7 @@ #include "sim/system.hh" using namespace std; +using namespace TheISA; BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu, HierParams *hier, Bus *pio_bus, const string &devicename) @@ -61,7 +62,7 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu, } -Fault * +Fault BadDevice::read(MemReqPtr &req, uint8_t *data) { @@ -69,7 +70,7 @@ BadDevice::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault BadDevice::write(MemReqPtr &req, const uint8_t *data) { panic("Device %s not imlpmented\n", devname); diff --git a/dev/baddev.hh b/dev/baddev.hh index b7b67e31a..c2a204c05 100644 --- a/dev/baddev.hh +++ b/dev/baddev.hh @@ -71,7 +71,7 @@ class BadDevice : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * On a write event we just panic aand hopefully print a @@ -80,7 +80,7 @@ class BadDevice : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Return how long this access will take. diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index a5cb0dfd8..56682a224 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -48,6 +48,7 @@ #include "sim/sim_object.hh" using namespace std; +using namespace TheISA; //// // Initialization and destruction @@ -390,7 +391,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data) } } -Fault * +Fault IdeController::read(MemReqPtr &req, uint8_t *data) { Addr offset; @@ -460,7 +461,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault IdeController::write(MemReqPtr &req, const uint8_t *data) { Addr offset; diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh index 72523f57c..0fbaf9207 100644 --- a/dev/ide_ctrl.hh +++ b/dev/ide_ctrl.hh @@ -213,7 +213,7 @@ class IdeController : public PciDev * @param data Return the field read. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Write to the mmapped I/O control registers. @@ -221,7 +221,7 @@ class IdeController : public PciDev * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Serialize this object to the given output stream. diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc index 9d8bb8825..41400c590 100644 --- a/dev/ide_disk.cc +++ b/dev/ide_disk.cc @@ -53,6 +53,7 @@ #include "arch/isa_traits.hh" using namespace std; +using namespace TheISA; IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys, int id, Tick delay) diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc index 93c9eedbf..2afebbded 100644 --- a/dev/isa_fake.cc +++ b/dev/isa_fake.cc @@ -45,6 +45,7 @@ #include "sim/system.hh" using namespace std; +using namespace TheISA; IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, HierParams *hier, Bus *pio_bus, Addr size) @@ -59,7 +60,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, } } -Fault * +Fault IsaFake::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", @@ -92,7 +93,7 @@ IsaFake::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault IsaFake::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x size=%d \n", diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh index 60ca5f90a..290b24b54 100644 --- a/dev/isa_fake.hh +++ b/dev/isa_fake.hh @@ -65,14 +65,14 @@ class IsaFake : public PioDevice * @param req The memory request. * @param data Where to put the data. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * All writes are simply ignored. * @param req The memory request. * @param data the data to not write. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Return how long this access will take. diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index c28615438..4b08d8497 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -84,6 +84,7 @@ const char *NsDmaState[] = using namespace std; using namespace Net; +using namespace TheISA; /////////////////////////////////////////////////////////////////////// // @@ -130,8 +131,6 @@ NSGigE::NSGigE(Params *p) } else if (p->payload_bus) panic("Must define a header bus if defining a payload bus"); - pioDelayWrite = p->pio_delay_write && pioInterface; - intrDelay = p->intr_delay; dmaReadDelay = p->dma_read_delay; dmaWriteDelay = p->dma_write_delay; @@ -558,7 +557,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data) * This reads the device registers, which are detailed in the NS83820 * spec sheet */ -Fault * +Fault NSGigE::read(MemReqPtr &req, uint8_t *data) { assert(ioEnable); @@ -787,7 +786,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault NSGigE::write(MemReqPtr &req, const uint8_t *data) { assert(ioEnable); @@ -804,13 +803,6 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data) } else if (daddr > 0x3FC) panic("Something is messed up!\n"); - if (pioDelayWrite) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; - if (cpu >= writeQueue.size()) - writeQueue.resize(cpu + 1); - writeQueue[cpu].push_back(RegWriteData(daddr, *(uint32_t *)data)); - } - if (req->size == sizeof(uint32_t)) { uint32_t reg = *(uint32_t *)data; uint16_t rfaddr; @@ -823,24 +815,20 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data) if (reg & CR_TXD) { txEnable = false; } else if (reg & CR_TXE) { - if (!pioDelayWrite) { - txEnable = true; + txEnable = true; - // the kernel is enabling the transmit machine - if (txState == txIdle) - txKick(); - } + // the kernel is enabling the transmit machine + if (txState == txIdle) + txKick(); } if (reg & CR_RXD) { rxEnable = false; } else if (reg & CR_RXE) { - if (!pioDelayWrite) { - rxEnable = true; + rxEnable = true; - if (rxState == rxIdle) - rxKick(); - } + if (rxState == rxIdle) + rxKick(); } if (reg & CR_TXR) @@ -2948,38 +2936,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion) Tick NSGigE::cacheAccess(MemReqPtr &req) { - Addr daddr = req->paddr & 0xfff; DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n", - req->paddr, daddr); - - if (!pioDelayWrite || !req->cmd.isWrite()) - return curTick + pioLatency; - - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; - std::list<RegWriteData> &wq = writeQueue[cpu]; - if (wq.empty()) - panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr); - - const RegWriteData &data = wq.front(); - if (data.daddr != daddr) - panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x", - cpu, data.daddr, daddr); - - if (daddr == CR) { - if ((data.value & (CR_TXD | CR_TXE)) == CR_TXE) { - txEnable = true; - if (txState == txIdle) - txKick(); - } - - if ((data.value & (CR_RXD | CR_RXE)) == CR_RXE) { - rxEnable = true; - if (rxState == rxIdle) - rxKick(); - } - } + req->paddr, req->paddr & 0xfff); - wq.pop_front(); return curTick + pioLatency; } @@ -3039,7 +2998,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param<Tick> dma_write_factor; Param<bool> dma_no_allocate; Param<Tick> pio_latency; - Param<bool> pio_delay_write; Param<Tick> intr_delay; Param<Tick> rx_delay; @@ -3080,7 +3038,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(dma_write_factor, "multiplier for dma writes"), INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"), INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"), - INIT_PARAM(pio_delay_write, ""), INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"), INIT_PARAM(rx_delay, "Receive Delay"), @@ -3125,7 +3082,6 @@ CREATE_SIM_OBJECT(NSGigE) params->dma_write_factor = dma_write_factor; params->dma_no_allocate = dma_no_allocate; params->pio_latency = pio_latency; - params->pio_delay_write = pio_delay_write; params->intr_delay = intr_delay; params->rx_delay = rx_delay; diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 181837c8d..cdd8e4b9e 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -236,15 +236,6 @@ class NSGigE : public PciDev uint32_t rxDescCnt; DmaState rxDmaState; - struct RegWriteData { - Addr daddr; - uint32_t value; - RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {} - }; - - std::vector<std::list<RegWriteData> > writeQueue; - bool pioDelayWrite; - bool extstsEnable; /** EEPROM State Machine */ @@ -382,7 +373,6 @@ class NSGigE : public PciDev Tick tx_delay; Tick rx_delay; Tick pio_latency; - bool pio_delay_write; bool dma_desc_free; bool dma_data_free; Tick dma_read_delay; @@ -405,8 +395,8 @@ class NSGigE : public PciDev virtual void writeConfig(int offset, int size, const uint8_t *data); virtual void readConfig(int offset, int size, uint8_t *data); - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); bool cpuIntrPending() const; void cpuIntrAck() { cpuIntrClear(); } diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 1175172c4..d55084fa5 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -47,6 +47,7 @@ #include "sim/system.hh" using namespace std; +using namespace TheISA; PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu, @@ -95,7 +96,7 @@ PciConfigAll::startup() } -Fault * +Fault PciConfigAll::read(MemReqPtr &req, uint8_t *data) { @@ -143,7 +144,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault PciConfigAll::write(MemReqPtr &req, const uint8_t *data) { Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh index 6df033286..c6a0241d8 100644 --- a/dev/pciconfigall.hh +++ b/dev/pciconfigall.hh @@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice * @param data Return the field read. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Write to PCI config spcae. If the device does not exit the simulator @@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Start up function to check if more than one person is using an interrupt line diff --git a/dev/pcidev.cc b/dev/pcidev.cc index c469e716a..a05ee3803 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -70,59 +70,59 @@ PciDev::PciDev(Params *p) p->configSpace->registerDevice(p->deviceNum, p->functionNum, this); } -Fault * +Fault PciDev::read(MemReqPtr &req, uint8_t *data) { return NoFault; } -Fault * +Fault PciDev::write(MemReqPtr &req, const uint8_t *data) { return NoFault; } -Fault * +Fault PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } diff --git a/dev/pcidev.hh b/dev/pcidev.hh index c8d9685c1..9427463bf 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -189,37 +189,37 @@ class PciDev : public DmaDevice */ PciDev(Params *params); - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); public: /** * Implement the read/write as BAR accesses */ - Fault * readBar(MemReqPtr &req, uint8_t *data); - Fault * writeBar(MemReqPtr &req, const uint8_t *data); + Fault readBar(MemReqPtr &req, uint8_t *data); + Fault writeBar(MemReqPtr &req, const uint8_t *data); public: /** * Read from a specific BAR */ - virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data); public: /** * Write to a specific BAR */ - virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data); public: /** @@ -257,7 +257,7 @@ class PciDev : public DmaDevice virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -inline Fault * +inline Fault PciDev::readBar(MemReqPtr &req, uint8_t *data) { if (isBAR(req->paddr, 0)) @@ -275,7 +275,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return MachineCheckFault; } -inline Fault * +inline Fault PciDev::writeBar(MemReqPtr &req, const uint8_t *data) { if (isBAR(req->paddr, 0)) diff --git a/dev/platform.cc b/dev/platform.cc index 58f94db7b..5b667b12c 100644 --- a/dev/platform.cc +++ b/dev/platform.cc @@ -31,6 +31,7 @@ #include "sim/sim_exit.hh" using namespace std; +using namespace TheISA; Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci) : SimObject(name), intrctrl(intctrl), pciconfig(pci) diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh index 6560e15c2..57f81c5a9 100644 --- a/dev/simple_disk.hh +++ b/dev/simple_disk.hh @@ -44,19 +44,19 @@ class PhysicalMemory; */ class SimpleDisk : public SimObject { -public: - typedef uint64_t baddr_t; + public: + typedef uint64_t baddr_t; -protected: - PhysicalMemory *physmem; - DiskImage *image; + protected: + PhysicalMemory *physmem; + DiskImage *image; -public: - SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img); - ~SimpleDisk(); + public: + SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img); + ~SimpleDisk(); - void read(Addr addr, baddr_t block, int count) const; - void write(Addr addr, baddr_t block, int count); + void read(Addr addr, baddr_t block, int count) const; + void write(Addr addr, baddr_t block, int count); }; #endif // __DEV_SIMPLE_DISK_HH__ diff --git a/dev/sinic.cc b/dev/sinic.cc index e79f80678..c499d2f49 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -50,6 +50,7 @@ #include "targetarch/vtophys.hh" using namespace Net; +using namespace TheISA; namespace Sinic { @@ -112,8 +113,6 @@ Device::Device(Params *p) p->dma_no_allocate); } else if (p->payload_bus) panic("must define a header bus if defining a payload bus"); - - pioDelayWrite = p->pio_delay_write && pioInterface; } Device::~Device() @@ -352,20 +351,17 @@ Device::prepareRead(int cpu, int index) void Device::prepareWrite(int cpu, int index) { - if (cpu >= writeQueue.size()) - writeQueue.resize(cpu + 1); - prepareIO(cpu, index); } /** * I/O read of device register */ -Fault * +Fault Device::read(MemReqPtr &req, uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault * fault = readBar(req, data); + Fault fault = readBar(req, data); if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", @@ -377,7 +373,7 @@ Device::read(MemReqPtr &req, uint8_t *data) return fault; } -Fault * +Fault Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; @@ -427,7 +423,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) /** * IPR read of device register */ -Fault * +Fault Device::iprRead(Addr daddr, int cpu, uint64_t &result) { if (!regValid(daddr)) @@ -457,11 +453,11 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result) /** * I/O write of device register */ -Fault * +Fault Device::write(MemReqPtr &req, const uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault * fault = writeBar(req, data); + Fault fault = writeBar(req, data); if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", @@ -473,7 +469,7 @@ Device::write(MemReqPtr &req, const uint8_t *data) return fault; } -Fault * +Fault Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; @@ -493,20 +489,16 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); - uint32_t reg32 = *(uint32_t *)data; + //uint32_t reg32 = *(uint32_t *)data; uint64_t reg64 = *(uint64_t *)data; DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? reg32 : reg64, daddr, + info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); - if (pioDelayWrite) - writeQueue[cpu].push_back(RegWriteData(daddr, reg64)); - - if (!pioDelayWrite || !info.delay_write) - regWrite(daddr, cpu, data); + regWrite(daddr, cpu, data); return NoFault; } @@ -1570,27 +1562,6 @@ Device::cacheAccess(MemReqPtr &req) DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n", req->cmd.toString(), req->paddr, bar, daddr); - if (!pioDelayWrite || !req->cmd.isWrite()) - return curTick + pioLatency; - - if (bar == 0) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; - std::list<RegWriteData> &wq = writeQueue[cpu]; - if (wq.empty()) - panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr); - - const RegWriteData &data = wq.front(); - if (data.daddr != daddr) - panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x", - cpu, data.daddr, daddr); - - const Regs::Info &info = regInfo(data.daddr); - if (info.delay_write) - regWrite(daddr, cpu, (uint8_t *)&data.value); - - wq.pop_front(); - } - return curTick + pioLatency; } @@ -1648,7 +1619,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param<Tick> dma_write_factor; Param<bool> dma_no_allocate; Param<Tick> pio_latency; - Param<bool> pio_delay_write; Param<Tick> intr_delay; Param<Tick> rx_delay; @@ -1692,7 +1662,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(dma_write_factor, "multiplier for dma writes"), INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"), INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"), - INIT_PARAM(pio_delay_write, ""), INIT_PARAM(intr_delay, "Interrupt Delay"), INIT_PARAM(rx_delay, "Receive Delay"), @@ -1740,7 +1709,6 @@ CREATE_SIM_OBJECT(Device) params->dma_write_factor = dma_write_factor; params->dma_no_allocate = dma_no_allocate; params->pio_latency = pio_latency; - params->pio_delay_write = pio_delay_write; params->intr_delay = intr_delay; params->tx_delay = tx_delay; diff --git a/dev/sinic.hh b/dev/sinic.hh index 7935a7cdc..97ebf4c30 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -271,29 +271,18 @@ class Device : public Base * Memory Interface */ public: - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); void prepareIO(int cpu, int index); void prepareRead(int cpu, int index); void prepareWrite(int cpu, int index); - Fault * iprRead(Addr daddr, int cpu, uint64_t &result); - Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); - Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); + Fault iprRead(Addr daddr, int cpu, uint64_t &result); + Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); - protected: - struct RegWriteData { - Addr daddr; - uint64_t value; - RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {} - }; - - std::vector<std::list<RegWriteData> > writeQueue; - - bool pioDelayWrite; - /** * Statistics */ @@ -349,7 +338,6 @@ class Device : public Base Bus *header_bus; Bus *payload_bus; Tick pio_latency; - bool pio_delay_write; PhysicalMemory *physmem; IntrControl *intctrl; bool rx_filter; diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index b7008b4e1..fc1f4c06b 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -157,8 +157,6 @@ struct Info uint8_t size; bool read; bool write; - bool delay_read; - bool delay_write; const char *name; }; @@ -167,33 +165,33 @@ struct Info inline const Regs::Info& regInfo(Addr daddr) { - static Regs::Info invalid = { 0, false, false, false, false, "invalid" }; + static Regs::Info invalid = { 0, false, false, "invalid" }; static Regs::Info info [] = { - { 4, true, true, false, false, "Config" }, - { 4, false, true, false, false, "Command" }, - { 4, true, true, false, false, "IntrStatus" }, - { 4, true, true, false, false, "IntrMask" }, - { 4, true, false, false, false, "RxMaxCopy" }, - { 4, true, false, false, false, "TxMaxCopy" }, - { 4, true, false, false, false, "RxMaxIntr" }, + { 4, true, true, "Config" }, + { 4, false, true, "Command" }, + { 4, true, true, "IntrStatus" }, + { 4, true, true, "IntrMask" }, + { 4, true, false, "RxMaxCopy" }, + { 4, true, false, "TxMaxCopy" }, + { 4, true, false, "RxMaxIntr" }, invalid, - { 4, true, false, false, false, "RxFifoSize" }, - { 4, true, false, false, false, "TxFifoSize" }, - { 4, true, false, false, false, "RxFifoMark" }, - { 4, true, false, false, false, "TxFifoMark" }, - { 8, true, true, false, true, "RxData" }, + { 4, true, false, "RxFifoSize" }, + { 4, true, false, "TxFifoSize" }, + { 4, true, false, "RxFifoMark" }, + { 4, true, false, "TxFifoMark" }, + { 8, true, true, "RxData" }, invalid, - { 8, true, false, false, false, "RxDone" }, + { 8, true, false, "RxDone" }, invalid, - { 8, true, false, false, false, "RxWait" }, + { 8, true, false, "RxWait" }, invalid, - { 8, true, true, false, true, "TxData" }, + { 8, true, true, "TxData" }, invalid, - { 8, true, false, false, false, "TxDone" }, + { 8, true, false, "TxDone" }, invalid, - { 8, true, false, false, false, "TxWait" }, + { 8, true, false, "TxWait" }, invalid, - { 8, true, false, false, false, "HwAddr" }, + { 8, true, false, "HwAddr" }, invalid, }; diff --git a/dev/tsunami.cc b/dev/tsunami.cc index 760848a00..58fc7434e 100644 --- a/dev/tsunami.cc +++ b/dev/tsunami.cc @@ -46,6 +46,8 @@ #include "sim/system.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; Tsunami::Tsunami(const string &name, System *s, IntrControl *ic, PciConfigAll *pci) diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 4cda9ec36..4dc4413a1 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -47,6 +47,8 @@ #include "sim/system.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, MemoryController *mmu, HierParams *hier, @@ -76,7 +78,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, tsunami->cchip = this; } -Fault * +Fault TsunamiCChip::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); @@ -190,7 +192,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n", diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh index dadbdb0e3..d88ad375f 100644 --- a/dev/tsunami_cchip.hh +++ b/dev/tsunami_cchip.hh @@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** @@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * post an RTC interrupt to the CPU diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 0d0d27570..e66d6653b 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -50,6 +50,8 @@ #include "mem/functional/memory_control.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i) : _name(name), event(t, i), addr(0) @@ -444,7 +446,7 @@ TsunamiIO::frequency() const return Clock::Frequency / clockInterval; } -Fault * +Fault TsunamiIO::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", @@ -521,7 +523,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault TsunamiIO::write(MemReqPtr &req, const uint8_t *data) { diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index 3b26ebfaa..b024ecd14 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Process a write to one of the devices we emulate. @@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Post an PIC interrupt to the CPU via the CChip diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index a4c04a79f..46efc3dfe 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -47,6 +47,8 @@ #include "sim/system.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, MemoryController *mmu, HierParams *hier, @@ -76,7 +78,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, tsunami->pchip = this; } -Fault * +Fault TsunamiPChip::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", @@ -165,7 +167,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x size=%d \n", diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh index ff888bea1..c1d95431b 100644 --- a/dev/tsunami_pchip.hh +++ b/dev/tsunami_pchip.hh @@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Process a write to the PChip. @@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Serialize this object to the given output stream. diff --git a/dev/uart.hh b/dev/uart.hh index 96c22025c..145b9ca9e 100644 --- a/dev/uart.hh +++ b/dev/uart.hh @@ -57,8 +57,8 @@ class Uart : public PioDevice Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p); - virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0; - virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0; + virtual Fault read(MemReqPtr &req, uint8_t *data) = 0; + virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0; /** diff --git a/dev/uart8250.cc b/dev/uart8250.cc index a2e782189..65bccee86 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -46,6 +46,7 @@ #include "sim/builder.hh" using namespace std; +using namespace TheISA; Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit) : Event(&mainEventQueue), uart(u) @@ -111,7 +112,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu, } -Fault * +Fault Uart8250::read(MemReqPtr &req, uint8_t *data) { Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); @@ -187,7 +188,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data) } -Fault * +Fault Uart8250::write(MemReqPtr &req, const uint8_t *data) { Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); diff --git a/dev/uart8250.hh b/dev/uart8250.hh index a0e2d344a..88abf8e24 100644 --- a/dev/uart8250.hh +++ b/dev/uart8250.hh @@ -82,8 +82,8 @@ class Uart8250 : public Uart Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency, Platform *p); - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** |