summaryrefslogtreecommitdiff
path: root/dev
diff options
context:
space:
mode:
Diffstat (limited to 'dev')
-rw-r--r--dev/alpha_console.cc4
-rw-r--r--dev/baddev.cc4
-rw-r--r--dev/etherdump.cc39
-rw-r--r--dev/etherdump.hh6
-rw-r--r--dev/etherpkt.hh12
-rw-r--r--dev/ide_ctrl.cc35
-rw-r--r--dev/ide_disk.cc14
-rw-r--r--dev/ns_gige.cc94
-rw-r--r--dev/ns_gige.hh18
-rw-r--r--dev/pciconfigall.cc4
-rw-r--r--dev/pcidev.cc61
-rw-r--r--dev/simconsole.cc31
-rw-r--r--dev/simconsole.hh2
-rw-r--r--dev/tsunami.hh5
-rw-r--r--dev/tsunami_cchip.cc4
-rw-r--r--dev/tsunami_io.cc4
-rw-r--r--dev/tsunami_pchip.cc4
-rw-r--r--dev/uart.cc6
18 files changed, 139 insertions, 208 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 680704b30..964ab442c 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -61,12 +61,12 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
HierParams *hier, Bus *bus)
: PioDevice(name), disk(d), console(cons), addr(a)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&AlphaConsole::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size);
+ pioInterface->addAddrRange(RangeSize(addr, size));
}
alphaAccess = new AlphaAccess;
diff --git a/dev/baddev.cc b/dev/baddev.cc
index 7c563e80a..73b082d47 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -50,12 +50,12 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, const string &devicename)
: PioDevice(name), addr(a), devname(devicename)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&BadDevice::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
}
}
diff --git a/dev/etherdump.cc b/dev/etherdump.cc
index 27817d456..485d5599c 100644
--- a/dev/etherdump.cc
+++ b/dev/etherdump.cc
@@ -42,11 +42,9 @@
using std::string;
-EtherDump::EtherDump(const string &name, const string &file, int max)
- : SimObject(name), maxlen(max)
+EtherDump::EtherDump(const string &name, std::ostream *_stream, int max)
+ : SimObject(name), stream(_stream), maxlen(max)
{
- if (!file.empty())
- stream.open(file.c_str());
}
#define DLT_EN10MB 1 // Ethernet (10Mb)
@@ -74,9 +72,6 @@ struct pcap_pkthdr {
void
EtherDump::init()
{
- if (!stream.is_open())
- return;
-
curtime = time(NULL);
s_freq = ticksPerSecond;
us_freq = ticksPerSecond / ULL(1000000);
@@ -91,7 +86,7 @@ EtherDump::init()
hdr.sigfigs = 0;
hdr.linktype = DLT_EN10MB;
- stream.write(reinterpret_cast<char *>(&hdr), sizeof(hdr));
+ stream->write(reinterpret_cast<char *>(&hdr), sizeof(hdr));
/*
* output an empty packet with the current time so that we know
@@ -103,9 +98,9 @@ EtherDump::init()
pkthdr.microseconds = 0;
pkthdr.caplen = 0;
pkthdr.len = 0;
- stream.write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
+ stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
- stream.flush();
+ stream->flush();
}
void
@@ -116,9 +111,9 @@ EtherDump::dumpPacket(PacketPtr &packet)
pkthdr.microseconds = (curTick / us_freq) % ULL(1000000);
pkthdr.caplen = std::min(packet->length, maxlen);
pkthdr.len = packet->length;
- stream.write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
- stream.write(reinterpret_cast<char *>(packet->data), pkthdr.caplen);
- stream.flush();
+ stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
+ stream->write(reinterpret_cast<char *>(packet->data), pkthdr.caplen);
+ stream->flush();
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
@@ -130,28 +125,14 @@ END_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDump)
- INIT_PARAM(file, "file to dump packets to"),
+ INIT_PARAM_DFLT(file, "file to dump packets to", "etherdump"),
INIT_PARAM_DFLT(maxlen, "max portion of packet data to dump", 96)
END_INIT_SIM_OBJECT_PARAMS(EtherDump)
CREATE_SIM_OBJECT(EtherDump)
{
- string filename;
- if (file.isValid()) {
- filename = file;
-
- if (filename[0] != '/' && !outputDirectory.empty())
- filename = outputDirectory + filename;
- } else {
- if (outputDirectory.empty()) {
- filename = "etherdump";
- } else {
- filename = outputDirectory + "etherdump";
- }
- }
-
- return new EtherDump(getInstanceName(), filename, maxlen);
+ return new EtherDump(getInstanceName(), makeOutputStream(file), maxlen);
}
REGISTER_SIM_OBJECT("EtherDump", EtherDump)
diff --git a/dev/etherdump.hh b/dev/etherdump.hh
index 62364359e..b127d05e2 100644
--- a/dev/etherdump.hh
+++ b/dev/etherdump.hh
@@ -43,7 +43,7 @@
class EtherDump : public SimObject
{
private:
- std::ofstream stream;
+ std::ostream *stream;
const int maxlen;
void dumpPacket(PacketPtr &packet);
void init();
@@ -53,9 +53,9 @@ class EtherDump : public SimObject
Tick us_freq;
public:
- EtherDump(const std::string &name, const std::string &file, int max);
+ EtherDump(const std::string &name, std::ostream *_stream, int max);
- inline void dump(PacketPtr &pkt) { if (stream.is_open()) dumpPacket(pkt); }
+ inline void dump(PacketPtr &pkt) { dumpPacket(pkt); }
};
#endif // __ETHERDUMP_H__
diff --git a/dev/etherpkt.hh b/dev/etherpkt.hh
index 9c5f00491..1b6e9858f 100644
--- a/dev/etherpkt.hh
+++ b/dev/etherpkt.hh
@@ -38,7 +38,6 @@
#include <assert.h>
#include "base/refcnt.hh"
-#include "base/inet.hh"
#include "sim/host.hh"
/*
@@ -58,17 +57,6 @@ class PacketData : public RefCounted
~PacketData() { if (data) delete [] data; }
public:
- const EthHdr *eth() const { return (const EthHdr *)data; }
- const IpHdr *ip() const {const EthHdr *h = eth(); return h ? h->ip() : 0;}
- const TcpHdr *tcp() const {const IpHdr *h = ip(); return h ? h->tcp() : 0;}
- const UdpHdr *udp() const {const IpHdr *h = ip(); return h ? h->udp() : 0;}
-
- EthHdr *eth() { return (EthHdr *)data; }
- IpHdr *ip() { EthHdr *h = eth(); return h ? h->ip() : 0; }
- TcpHdr *tcp() { IpHdr *h = ip(); return h ? h->tcp() : 0; }
- UdpHdr *udp() { IpHdr *h = ip(); return h ? h->udp() : 0; }
-
- public:
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index ec881ed15..d08e61fbf 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -63,9 +63,6 @@ IdeController::IdeController(const string &name, IntrControl *ic,
Bus *host_bus, Tick pio_latency, HierParams *hier)
: PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
{
- // put back pointer into Tsunami
- tsunami->disk_controller = this;
-
// initialize the PIO interface addresses
pri_cmd_addr = 0;
pri_cmd_size = BARSize[0];
@@ -377,8 +374,8 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
if (BARAddrs[0] != 0) {
pri_cmd_addr = BARAddrs[0];
if (pioInterface)
- pioInterface->addAddrRange(pri_cmd_addr,
- pri_cmd_addr + pri_cmd_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_cmd_addr,
+ pri_cmd_size));
pri_cmd_addr &= PA_UNCACHED_MASK;
}
@@ -388,8 +385,8 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
if (BARAddrs[1] != 0) {
pri_ctrl_addr = BARAddrs[1];
if (pioInterface)
- pioInterface->addAddrRange(pri_ctrl_addr,
- pri_ctrl_addr + pri_ctrl_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_ctrl_addr,
+ pri_ctrl_size));
pri_ctrl_addr &= PA_UNCACHED_MASK;
}
@@ -399,8 +396,8 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
if (BARAddrs[2] != 0) {
sec_cmd_addr = BARAddrs[2];
if (pioInterface)
- pioInterface->addAddrRange(sec_cmd_addr,
- sec_cmd_addr + sec_cmd_size - 1);
+ pioInterface->addAddrRange(RangeSize(sec_cmd_addr,
+ sec_cmd_size));
sec_cmd_addr &= PA_UNCACHED_MASK;
}
@@ -410,8 +407,8 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
if (BARAddrs[3] != 0) {
sec_ctrl_addr = BARAddrs[3];
if (pioInterface)
- pioInterface->addAddrRange(sec_ctrl_addr,
- sec_ctrl_addr + sec_ctrl_size - 1);
+ pioInterface->addAddrRange(RangeSize(sec_ctrl_addr,
+ sec_ctrl_size));
sec_ctrl_addr &= PA_UNCACHED_MASK;
}
@@ -421,7 +418,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
if (BARAddrs[4] != 0) {
bmi_addr = BARAddrs[4];
if (pioInterface)
- pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
+ pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
bmi_addr &= PA_UNCACHED_MASK;
}
@@ -675,15 +672,11 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(cmd_in_progress, 4);
if (pioInterface) {
- pioInterface->addAddrRange(pri_cmd_addr, pri_cmd_addr +
- pri_cmd_size - 1);
- pioInterface->addAddrRange(pri_ctrl_addr, pri_ctrl_addr +
- pri_ctrl_size - 1);
- pioInterface->addAddrRange(sec_cmd_addr, sec_cmd_addr +
- sec_cmd_size - 1);
- pioInterface->addAddrRange(sec_ctrl_addr, sec_ctrl_addr +
- sec_ctrl_size - 1);
- pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size));
+ pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size));
+ pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size));
+ pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size));
+ pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
}
}
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index f4e7c1ef1..f3760bd5e 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -35,7 +35,6 @@
#include <deque>
#include <string>
-#include "arch/alpha/pmap.h"
#include "base/cprintf.hh" // csprintf
#include "base/trace.hh"
#include "dev/disk_image.hh"
@@ -51,6 +50,7 @@
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "sim/universe.hh"
+#include "targetarch/isa_traits.hh"
using namespace std;
@@ -188,14 +188,14 @@ IdeDisk::bytesInDmaPage(Addr curAddr, uint32_t bytesLeft)
uint32_t bytesInPage = 0;
// First calculate how many bytes could be in the page
- if (bytesLeft > ALPHA_PGBYTES)
- bytesInPage = ALPHA_PGBYTES;
+ if (bytesLeft > TheISA::PageBytes)
+ bytesInPage = TheISA::PageBytes;
else
bytesInPage = bytesLeft;
// Next, see if we have crossed a page boundary, and adjust
Addr upperBound = curAddr + bytesInPage;
- Addr pageBound = alpha_trunc_page(curAddr) + ALPHA_PGBYTES;
+ Addr pageBound = TheISA::TruncPage(curAddr) + TheISA::PageBytes;
assert(upperBound >= curAddr && "DMA read wraps around address space!\n");
@@ -510,7 +510,7 @@ IdeDisk::dmaWriteDone()
// setup the initial page and DMA address
curAddr = curPrd.getBaseAddr();
- pageAddr = alpha_trunc_page(curAddr);
+ pageAddr = TheISA::TruncPage(curAddr);
dmaAddr = pciToDma(curAddr);
// clear out the data buffer
@@ -518,14 +518,14 @@ IdeDisk::dmaWriteDone()
while (bytesRead < curPrd.getByteCount()) {
// see if we have crossed into a new page
- if (pageAddr != alpha_trunc_page(curAddr)) {
+ if (pageAddr != TheISA::TruncPage(curAddr)) {
// write the data to memory
memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
(void *)(dataBuffer + (bytesRead - bytesInPage)),
bytesInPage);
// update the DMA address and page address
- pageAddr = alpha_trunc_page(curAddr);
+ pageAddr = TheISA::TruncPage(curAddr);
dmaAddr = pciToDma(curAddr);
bytesInPage = 0;
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 7260ecde4..4d0b93ab9 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -86,7 +86,7 @@ const char *NsDmaState[] =
};
using namespace std;
-
+using namespace Net;
///////////////////////////////////////////////////////////////////////
//
@@ -99,7 +99,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
- uint32_t func, bool rx_filter, const int eaddr[6],
+ uint32_t func, bool rx_filter, EthAddr eaddr,
uint32_t tx_fifo_size, uint32_t rx_fifo_size)
: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), ioEnable(false),
maxTxFifoSize(tx_fifo_size), maxRxFifoSize(rx_fifo_size),
@@ -119,8 +119,6 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
physmem(pmem), intctrl(i), intrTick(0), cpuPendingIntr(false),
intrEvent(0), interface(0)
{
- tsunami->ethernet = this;
-
if (header_bus) {
pioInterface = newPioInterface(name, hier, header_bus, this,
&NSGigE::cacheAccess);
@@ -151,12 +149,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
dmaWriteFactor = dma_write_factor;
regsReset();
- rom.perfectMatch[0] = eaddr[0];
- rom.perfectMatch[1] = eaddr[1];
- rom.perfectMatch[2] = eaddr[2];
- rom.perfectMatch[3] = eaddr[3];
- rom.perfectMatch[4] = eaddr[4];
- rom.perfectMatch[5] = eaddr[5];
+ memcpy(&rom.perfectMatch, eaddr.bytes(), ETH_ADDR_LEN);
}
NSGigE::~NSGigE()
@@ -344,8 +337,7 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
case PCI0_BASE_ADDR0:
if (BARAddrs[0] != 0) {
if (pioInterface)
- pioInterface->addAddrRange(BARAddrs[0],
- BARAddrs[0] + BARSize[0] - 1);
+ pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
BARAddrs[0] &= PA_UNCACHED_MASK;
}
@@ -353,8 +345,7 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
case PCI0_BASE_ADDR1:
if (BARAddrs[1] != 0) {
if (pioInterface)
- pioInterface->addAddrRange(BARAddrs[1],
- BARAddrs[1] + BARSize[1] - 1);
+ pioInterface->addAddrRange(RangeSize(BARAddrs[1], BARSize[1]));
BARAddrs[1] &= PA_UNCACHED_MASK;
}
@@ -1341,10 +1332,10 @@ NSGigE::rxKick()
#if TRACING_ON
if (DTRACE(Ethernet)) {
- const IpHdr *ip = rxPacket->ip();
+ IpPtr ip(rxPacket);
if (ip) {
DPRINTF(Ethernet, "ID is %d\n", ip->id());
- const TcpHdr *tcp = rxPacket->tcp();
+ TcpPtr tcp(ip);
if (tcp) {
DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
tcp->sport(), tcp->dport());
@@ -1403,36 +1394,38 @@ NSGigE::rxKick()
*/
if (rxFilterEnable) {
rxDescCache.cmdsts &= ~CMDSTS_DEST_MASK;
- EthHdr *eth = rxFifoFront()->eth();
- if (eth->unicast())
+ const EthAddr &dst = rxFifoFront()->dst();
+ if (dst->unicast())
rxDescCache.cmdsts |= CMDSTS_DEST_SELF;
- if (eth->multicast())
+ if (dst->multicast())
rxDescCache.cmdsts |= CMDSTS_DEST_MULTI;
- if (eth->broadcast())
+ if (dst->broadcast())
rxDescCache.cmdsts |= CMDSTS_DEST_MASK;
}
#endif
- if (extstsEnable && rxPacket->ip()) {
+ IpPtr ip(rxPacket);
+ if (extstsEnable && ip) {
rxDescCache.extsts |= EXTSTS_IPPKT;
rxIpChecksums++;
- IpHdr *ip = rxPacket->ip();
- if (ip->ip_cksum() != 0) {
+ if (cksum(ip) != 0) {
DPRINTF(EthernetCksum, "Rx IP Checksum Error\n");
rxDescCache.extsts |= EXTSTS_IPERR;
}
- if (rxPacket->tcp()) {
+ TcpPtr tcp(ip);
+ UdpPtr udp(ip);
+ if (tcp) {
rxDescCache.extsts |= EXTSTS_TCPPKT;
rxTcpChecksums++;
- if (ip->tu_cksum() != 0) {
+ if (cksum(tcp) != 0) {
DPRINTF(EthernetCksum, "Rx TCP Checksum Error\n");
rxDescCache.extsts |= EXTSTS_TCPERR;
}
- } else if (rxPacket->udp()) {
+ } else if (udp) {
rxDescCache.extsts |= EXTSTS_UDPPKT;
rxUdpChecksums++;
- if (ip->tu_cksum() != 0) {
+ if (cksum(udp) != 0) {
DPRINTF(EthernetCksum, "Rx UDP Checksum Error\n");
rxDescCache.extsts |= EXTSTS_UDPERR;
}
@@ -1550,10 +1543,10 @@ NSGigE::transmit()
if (interface->sendPacket(txFifo.front())) {
#if TRACING_ON
if (DTRACE(Ethernet)) {
- const IpHdr *ip = txFifo.front()->ip();
+ IpPtr ip(txFifo.front());
if (ip) {
DPRINTF(Ethernet, "ID is %d\n", ip->id());
- const TcpHdr *tcp = txFifo.front()->tcp();
+ TcpPtr tcp(ip);
if (tcp) {
DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
tcp->sport(), tcp->dport());
@@ -1816,21 +1809,21 @@ NSGigE::txKick()
DPRINTF(EthernetSM, "This packet is done, let's wrap it up\n");
/* deal with the the packet that just finished */
if ((regs.vtcr & VTCR_PPCHK) && extstsEnable) {
- IpHdr *ip = txPacket->ip();
+ IpPtr ip(txPacket);
if (txDescCache.extsts & EXTSTS_UDPPKT) {
- UdpHdr *udp = txPacket->udp();
+ UdpPtr udp(ip);
udp->sum(0);
- udp->sum(ip->tu_cksum());
+ udp->sum(cksum(udp));
txUdpChecksums++;
} else if (txDescCache.extsts & EXTSTS_TCPPKT) {
- TcpHdr *tcp = txPacket->tcp();
+ TcpPtr tcp(ip);
tcp->sum(0);
- tcp->sum(ip->tu_cksum());
+ tcp->sum(cksum(tcp));
txTcpChecksums++;
}
if (txDescCache.extsts & EXTSTS_IPPKT) {
ip->sum(0);
- ip->sum(ip->ip_cksum());
+ ip->sum(cksum(ip));
txIpChecksums++;
}
}
@@ -1989,31 +1982,31 @@ NSGigE::transferDone()
}
bool
-NSGigE::rxFilter(PacketPtr packet)
+NSGigE::rxFilter(PacketPtr &packet)
{
+ EthPtr eth = packet;
bool drop = true;
string type;
- EthHdr *eth = packet->eth();
- if (eth->unicast()) {
+ const EthAddr &dst = eth->dst();
+ if (dst.unicast()) {
// If we're accepting all unicast addresses
if (acceptUnicast)
drop = false;
// If we make a perfect match
- if (acceptPerfect &&
- memcmp(rom.perfectMatch, packet->data, EADDR_LEN) == 0)
+ if (acceptPerfect && dst == rom.perfectMatch)
drop = false;
if (acceptArp && eth->type() == ETH_TYPE_ARP)
drop = false;
- } else if (eth->broadcast()) {
+ } else if (dst.broadcast()) {
// if we're accepting broadcasts
if (acceptBroadcast)
drop = false;
- } else if (eth->multicast()) {
+ } else if (dst.multicast()) {
// if we're accepting all multicasts
if (acceptMulticast)
drop = false;
@@ -2029,7 +2022,7 @@ NSGigE::rxFilter(PacketPtr packet)
}
bool
-NSGigE::recvPacket(PacketPtr packet)
+NSGigE::recvPacket(PacketPtr &packet)
{
rxBytes += packet->length;
rxPackets++;
@@ -2122,7 +2115,7 @@ NSGigE::serialize(ostream &os)
SERIALIZE_SCALAR(regs.taner);
SERIALIZE_SCALAR(regs.tesr);
- SERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
+ SERIALIZE_ARRAY(rom.perfectMatch, ETH_ADDR_LEN);
SERIALIZE_SCALAR(ioEnable);
@@ -2279,7 +2272,7 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(regs.taner);
UNSERIALIZE_SCALAR(regs.tesr);
- UNSERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
+ UNSERIALIZE_ARRAY(rom.perfectMatch, ETH_ADDR_LEN);
UNSERIALIZE_SCALAR(ioEnable);
@@ -2410,8 +2403,8 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
* re-add addrRanges to bus bridges
*/
if (pioInterface) {
- pioInterface->addAddrRange(BARAddrs[0], BARAddrs[0] + BARSize[0] - 1);
- pioInterface->addAddrRange(BARAddrs[1], BARAddrs[1] + BARSize[1] - 1);
+ pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
+ pioInterface->addAddrRange(RangeSize(BARAddrs[1], BARSize[1]));
}
}
@@ -2519,16 +2512,13 @@ END_INIT_SIM_OBJECT_PARAMS(NSGigE)
CREATE_SIM_OBJECT(NSGigE)
{
- int eaddr[6];
- sscanf(((string)hardware_address).c_str(), "%x:%x:%x:%x:%x:%x",
- &eaddr[0], &eaddr[1], &eaddr[2], &eaddr[3], &eaddr[4], &eaddr[5]);
-
return new NSGigE(getInstanceName(), intr_ctrl, intr_delay,
physmem, tx_delay, rx_delay, mmu, hier, header_bus,
payload_bus, pio_latency, dma_desc_free, dma_data_free,
dma_read_delay, dma_write_delay, dma_read_factor,
dma_write_factor, configspace, configdata,
- tsunami, pci_bus, pci_dev, pci_func, rx_filter, eaddr,
+ tsunami, pci_bus, pci_dev, pci_func, rx_filter,
+ EthAddr((string)hardware_address),
tx_fifo_size, rx_fifo_size);
}
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index b7838cf6f..60dcf3fc2 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -31,9 +31,10 @@
* DP83820 ethernet controller
*/
-#ifndef __NS_GIGE_HH__
-#define __NS_GIGE_HH__
+#ifndef __DEV_NS_GIGE_HH__
+#define __DEV_NS_GIGE_HH__
+#include "base/inet.hh"
#include "base/statistics.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
@@ -44,9 +45,6 @@
#include "mem/bus/bus.hh"
#include "sim/eventq.hh"
-/** length of ethernet address in bytes */
-#define EADDR_LEN 6
-
/**
* Ethernet device registers
*/
@@ -90,7 +88,7 @@ struct dp_rom {
* for perfect match memory.
* the linux driver doesn't use any other ROM
*/
- uint8_t perfectMatch[EADDR_LEN];
+ uint8_t perfectMatch[ETH_ADDR_LEN];
};
class IntrControl;
@@ -302,7 +300,7 @@ class NSGigE : public PciDev
* receive address filter
*/
bool rxFilterEnable;
- bool rxFilter(PacketPtr packet);
+ bool rxFilter(PacketPtr &packet);
bool acceptBroadcast;
bool acceptMulticast;
bool acceptUnicast;
@@ -339,7 +337,7 @@ class NSGigE : public PciDev
bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
- uint32_t func, bool rx_filter, const int eaddr[6],
+ uint32_t func, bool rx_filter, Net::EthAddr eaddr,
uint32_t tx_fifo_size, uint32_t rx_fifo_size);
~NSGigE();
@@ -352,7 +350,7 @@ class NSGigE : public PciDev
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
- bool recvPacket(PacketPtr packet);
+ bool recvPacket(PacketPtr &packet);
void transferDone();
void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
@@ -403,4 +401,4 @@ class NSGigEInt : public EtherInt
virtual void sendDone() { dev->transferDone(); }
};
-#endif // __NS_GIGE_HH__
+#endif // __DEV_NS_GIGE_HH__
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 740a9b4ac..6fee30c10 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -50,12 +50,12 @@ PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, Tick pio_latency)
: PioDevice(name), addr(a)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&PciConfigAll::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
}
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index 7b13aac80..f0ceb40f2 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -129,7 +129,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
case PCI0_INTERRUPT_LINE:
case PCI_CACHE_LINE_SIZE:
case PCI_LATENCY_TIMER:
- *(uint8_t *)&config.data[offset] = byte_value;
+ *(uint8_t *)&config.data[offset] = htoa(byte_value);
break;
default:
@@ -142,7 +142,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
case PCI_COMMAND:
case PCI_STATUS:
case PCI_CACHE_LINE_SIZE:
- *(uint16_t *)&config.data[offset] = half_value;
+ *(uint16_t *)&config.data[offset] = htoa(half_value);
break;
default:
@@ -166,67 +166,59 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
// to size of memory it needs
if (word_value == 0xffffffff) {
// This is I/O Space, bottom two bits are read only
- if (config.data[offset] & 0x1) {
- *(uint32_t *)&config.data[offset] =
+ if (htoa(config.data[offset]) & 0x1) {
+ *(uint32_t *)&config.data[offset] = htoa(
~(BARSize[barnum] - 1) |
- (config.data[offset] & 0x3);
+ (htoa(config.data[offset]) & 0x3));
} else {
// This is memory space, bottom four bits are read only
- *(uint32_t *)&config.data[offset] =
+ *(uint32_t *)&config.data[offset] = htoa(
~(BARSize[barnum] - 1) |
- (config.data[offset] & 0xF);
+ (htoa(config.data[offset]) & 0xF));
}
} else {
// This is I/O Space, bottom two bits are read only
- if(config.data[offset] & 0x1) {
- *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
- (config.data[offset] & 0x3);
+ if(htoa(config.data[offset]) & 0x1) {
+ *(uint32_t *)&config.data[offset] = htoa((word_value & ~0x3) |
+ (htoa(config.data[offset]) & 0x3));
if (word_value & ~0x1) {
Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
- Addr base_size = BARSize[barnum]-1;
+ Addr base_size = BARSize[barnum];
// It's never been set
if (BARAddrs[barnum] == 0)
mmu->add_child((FunctionalMemory *)this,
- Range<Addr>(base_addr,
- base_addr + base_size));
+ RangeSize(base_addr, base_size));
else
mmu->update_child((FunctionalMemory *)this,
- Range<Addr>(BARAddrs[barnum],
- BARAddrs[barnum] +
- base_size),
- Range<Addr>(base_addr,
- base_addr +
- base_size));
+ RangeSize(BARAddrs[barnum],
+ base_size),
+ RangeSize(base_addr, base_size));
BARAddrs[barnum] = base_addr;
}
} else {
// This is memory space, bottom four bits are read only
- *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
- (config.data[offset] & 0xF);
+ *(uint32_t *)&config.data[offset] = htoa((word_value & ~0xF) |
+ (htoa(config.data[offset]) & 0xF));
if (word_value & ~0x3) {
Addr base_addr = (word_value & ~0x3) +
TSUNAMI_PCI0_MEMORY;
- Addr base_size = BARSize[barnum]-1;
+ Addr base_size = BARSize[barnum];
// It's never been set
if (BARAddrs[barnum] == 0)
mmu->add_child((FunctionalMemory *)this,
- Range<Addr>(base_addr,
- base_addr + base_size));
+ RangeSize(base_addr, base_size));
else
mmu->update_child((FunctionalMemory *)this,
- Range<Addr>(BARAddrs[barnum],
- BARAddrs[barnum] +
- base_size),
- Range<Addr>(base_addr,
- base_addr +
- base_size));
+ RangeSize(BARAddrs[barnum],
+ base_size),
+ RangeSize(base_addr, base_size));
BARAddrs[barnum] = base_addr;
}
@@ -238,14 +230,14 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
if (word_value == 0xfffffffe)
*(uint32_t *)&config.data[offset] = 0xffffffff;
else
- *(uint32_t *)&config.data[offset] = word_value;
+ *(uint32_t *)&config.data[offset] = htoa(word_value);
break;
case PCI_COMMAND:
// This could also clear some of the error bits in the Status
// register. However they should never get set, so lets ignore
// it for now
- *(uint16_t *)&config.data[offset] = half_value;
+ *(uint16_t *)&config.data[offset] = htoa(half_value);
break;
default:
@@ -273,10 +265,7 @@ PciDev::unserialize(Checkpoint *cp, const std::string &section)
// Add the MMU mappings for the BARs
for (int i=0; i < 6; i++) {
if (BARAddrs[i] != 0)
- mmu->add_child((FunctionalMemory *)this,
- Range<Addr>(BARAddrs[i],
- BARAddrs[i] +
- BARSize[i] - 1));
+ mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
}
}
diff --git a/dev/simconsole.cc b/dev/simconsole.cc
index a15057402..b2afb3f84 100644
--- a/dev/simconsole.cc
+++ b/dev/simconsole.cc
@@ -72,27 +72,22 @@ SimConsole::Event::process(int revent)
cons->detach();
}
-SimConsole::SimConsole(const string &name, const string &file, int num)
+SimConsole::SimConsole(const string &name, std::ostream *os, int num)
: SimObject(name), event(NULL), number(num), in_fd(-1), out_fd(-1),
- listener(NULL), txbuf(16384), rxbuf(16384), outfile(NULL)
+ listener(NULL), txbuf(16384), rxbuf(16384), outfile(os)
#if TRACING_ON == 1
, linebuf(16384)
#endif
{
- if (!file.empty())
- outfile = new ofstream(file.c_str());
-
if (outfile)
outfile->setf(ios::unitbuf);
-
}
SimConsole::~SimConsole()
{
close();
-
if (outfile)
- delete outfile;
+ closeOutputStream(outfile);
}
void
@@ -311,7 +306,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
INIT_PARAM(listener, "console listener"),
INIT_PARAM(intr_control, "interrupt controller"),
- INIT_PARAM_DFLT(output, "file to dump output to", ""),
+ INIT_PARAM(output, "file to dump output to"),
INIT_PARAM_DFLT(append_name, "append name() to filename", true),
INIT_PARAM_DFLT(number, "console number", 0)
@@ -319,18 +314,18 @@ END_INIT_SIM_OBJECT_PARAMS(SimConsole)
CREATE_SIM_OBJECT(SimConsole)
{
- string filename = output;
- if (filename.empty()) {
- if (!outputDirectory.empty())
- filename = outputDirectory + getInstanceName();
+ string filename;
+
+ if (!output.isValid()) {
+ filename = getInstanceName();
+ } else if (append_name) {
+ filename = (string)output + "." + getInstanceName();
} else {
- if (append_name)
- filename += "." + getInstanceName();
- if (!outputDirectory.empty())
- filename = outputDirectory + filename;
+ filename = output;
}
- SimConsole *console = new SimConsole(getInstanceName(), filename, number);
+ SimConsole *console = new SimConsole(getInstanceName(),
+ makeOutputStream(filename), number);
((ConsoleListener *)listener)->add(console);
return console;
diff --git a/dev/simconsole.hh b/dev/simconsole.hh
index 138e2e36a..c5a281834 100644
--- a/dev/simconsole.hh
+++ b/dev/simconsole.hh
@@ -70,7 +70,7 @@ class SimConsole : public SimObject
ConsoleListener *listener;
public:
- SimConsole(const std::string &name, const std::string &file, int num);
+ SimConsole(const std::string &name, std::ostream *os, int num);
~SimConsole();
protected:
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index df804956a..0a7fdbcd9 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -62,12 +62,9 @@ class Tsunami : public Platform
/** Pointer to the system */
System *system;
+
/** Pointer to the TsunamiIO device which has the RTC */
TsunamiIO *io;
- /** Pointer to the disk controller device */
- IdeController *disk_controller;
- /** Pointer to the ethernet controller device */
- NSGigE *ethernet;
/** Pointer to the Tsunami CChip.
* The chip contains some configuration information and
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index b43bb13bd..20b39f21f 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -53,7 +53,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
Tick pio_latency)
: PioDevice(name), addr(a), tsunami(t)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
for(int i=0; i < Tsunami::Max_CPUs; i++) {
dim[i] = 0;
@@ -66,7 +66,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiCChip::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
}
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 105e3b5b7..fab1b4b38 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -164,12 +164,12 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
Tick pio_latency)
: PioDevice(name), addr(a), tsunami(t), rtc(t)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiIO::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
}
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index 89940fb5a..4c94d12af 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -53,7 +53,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
Bus *bus, Tick pio_latency)
: PioDevice(name), addr(a), tsunami(t)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
for (int i = 0; i < 4; i++) {
wsba[i] = 0;
@@ -64,7 +64,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiPChip::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
}
diff --git a/dev/uart.cc b/dev/uart.cc
index fca856d5d..b71ab2d44 100644
--- a/dev/uart.cc
+++ b/dev/uart.cc
@@ -92,13 +92,13 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
: PioDevice(name), addr(a), size(s), cons(c), txIntrEvent(this, TX_INT),
rxIntrEvent(this, RX_INT), platform(p)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&Uart::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
}
@@ -287,7 +287,7 @@ Uart::write(MemReqPtr &req, const uint8_t *data)
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // write byte
- cons->out(*(uint64_t *)data);
+ cons->out(*(uint8_t *)data);
platform->clearConsoleInt();
status &= ~TX_INT;
if (UART_IER_THRI & IER)
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-22 05:16:44 +0000