diff options
Diffstat (limited to 'dev')
| -rw-r--r-- | dev/alpha_console.cc | 23 | ||||
| -rw-r--r-- | dev/alpha_console.hh | 3 | ||||
| -rw-r--r-- | dev/baddev.cc | 67 | ||||
| -rw-r--r-- | dev/baddev.hh | 49 | ||||
| -rw-r--r-- | dev/io_device.cc | 30 | ||||
| -rw-r--r-- | dev/io_device.hh | 24 | ||||
| -rw-r--r-- | dev/isa_fake.cc | 134 | ||||
| -rw-r--r-- | dev/isa_fake.hh | 35 | ||||
| -rw-r--r-- | dev/pciconfigall.cc | 197 | ||||
| -rw-r--r-- | dev/pciconfigall.hh | 31 | ||||
| -rw-r--r-- | dev/platform.cc | 4 | ||||
| -rw-r--r-- | dev/platform.hh | 3 | ||||
| -rw-r--r-- | dev/tsunami.cc | 13 | ||||
| -rw-r--r-- | dev/tsunami.hh | 6 | ||||
| -rw-r--r-- | dev/tsunami_cchip.cc | 539 | ||||
| -rw-r--r-- | dev/tsunami_cchip.hh | 52 | ||||
| -rw-r--r-- | dev/tsunami_io.cc | 380 | ||||
| -rw-r--r-- | dev/tsunami_io.hh | 58 | ||||
| -rw-r--r-- | dev/tsunami_pchip.cc | 392 | ||||
| -rw-r--r-- | dev/tsunami_pchip.hh | 61 | ||||
| -rw-r--r-- | dev/uart8250.cc | 14 |
21 files changed, 968 insertions, 1147 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 8c097fdd0..fde8af6ae 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -72,12 +72,12 @@ AlphaConsole::AlphaConsole(Params *p) alphaAccess->inputChar = 0; bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack)); - system->setAlphaAccess(pioAddr); } void AlphaConsole::startup() { + system->setAlphaAccess(pioAddr); alphaAccess->numCPUs = system->getNumCPUs(); alphaAccess->kernStart = system->getKernelStart(); alphaAccess->kernEnd = system->getKernelEnd(); @@ -87,15 +87,6 @@ AlphaConsole::startup() alphaAccess->intrClockFrequency = params()->platform->intrFrequency(); } -void -AlphaConsole::addressRanges(AddrRangeList &range_list) -{ - assert(pioSize != 0); - range_list.clear(); - range_list.push_back(RangeSize(pioAddr, sizeof(struct AlphaAccess))); -} - - Tick AlphaConsole::read(Packet &pkt) { @@ -120,8 +111,7 @@ AlphaConsole::read(Packet &pkt) if (!pkt.data) { data32 = new uint32_t; pkt.data = (uint8_t*)data32; - } - else + } else data32 = (uint32_t*)pkt.data; switch (daddr) @@ -150,8 +140,7 @@ AlphaConsole::read(Packet &pkt) if (!pkt.data) { data64 = new uint64_t; pkt.data = (uint8_t*)data64; - } - else + } else data64 = (uint64_t*)pkt.data; switch (daddr) { @@ -327,7 +316,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) SimObjectParam<SimConsole *> sim_console; SimObjectParam<SimpleDisk *> disk; - Param<Addr> addr; + Param<Addr> pio_addr; SimObjectParam<AlphaSystem *> system; SimObjectParam<BaseCPU *> cpu; SimObjectParam<Platform *> platform; @@ -339,7 +328,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) INIT_PARAM(sim_console, "The Simulator Console"), INIT_PARAM(disk, "Simple Disk"), - INIT_PARAM(addr, "Device Address"), + INIT_PARAM(pio_addr, "Device Address"), INIT_PARAM(system, "system object"), INIT_PARAM(cpu, "Processor"), INIT_PARAM(platform, "platform"), @@ -352,7 +341,7 @@ CREATE_SIM_OBJECT(AlphaConsole) AlphaConsole::Params *p = new AlphaConsole::Params; p->name = getInstanceName(); p->platform = platform; - p->pio_addr = addr; + p->pio_addr = pio_addr; p->pio_delay = pio_latency; p->cons = sim_console; p->disk = disk; diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 0435feb89..05aec5ec1 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -119,9 +119,6 @@ class AlphaConsole : public BasicPioDevice virtual Tick read(Packet &pkt); virtual Tick write(Packet &pkt); - /** Address ranges this device is sensitive to. */ - virtual void addressRanges(AddrRangeList &range_list); - /** * standard serialization routines for checkpointing */ diff --git a/dev/baddev.cc b/dev/baddev.cc index 87d683a5d..dcabdbe0a 100644 --- a/dev/baddev.cc +++ b/dev/baddev.cc @@ -35,82 +35,63 @@ #include <vector> #include "base/trace.hh" -#include "cpu/exec_context.hh" #include "dev/baddev.hh" #include "dev/platform.hh" -#include "mem/bus/bus.hh" -#include "mem/bus/pio_interface.hh" -#include "mem/bus/pio_interface_impl.hh" -#include "mem/functional/memory_control.hh" +#include "mem/port.hh" #include "sim/builder.hh" #include "sim/system.hh" using namespace std; using namespace TheISA; -BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *pio_bus, const string &devicename) - : PioDevice(name, NULL), addr(a), devname(devicename) +BadDevice::BadDevice(Params *p) + : BasicPioDevice(p), devname(p->device_name) { - mmu->add_child(this, RangeSize(addr, size)); - - if (pio_bus) { - pioInterface = newPioInterface(name, hier, pio_bus, this, - &BadDevice::cacheAccess); - pioInterface->addAddrRange(RangeSize(addr, size)); - } - + pioSize = 0xf; } -Fault -BadDevice::read(MemReqPtr &req, uint8_t *data) -{ - - panic("Device %s not imlpmented\n", devname); - return NoFault; -} - -Fault -BadDevice::write(MemReqPtr &req, const uint8_t *data) +Tick +BadDevice::read(Packet &pkt) { panic("Device %s not imlpmented\n", devname); - return NoFault; } Tick -BadDevice::cacheAccess(MemReqPtr &req) +BadDevice::write(Packet &pkt) { - return curTick; + panic("Device %s not imlpmented\n", devname); } BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice) + Param<string> devicename; + Param<Addr> pio_addr; + SimObjectParam<System *> system; SimObjectParam<Platform *> platform; - SimObjectParam<MemoryController *> mmu; - Param<Addr> addr; - SimObjectParam<HierParams *> hier; - SimObjectParam<Bus*> pio_bus; Param<Tick> pio_latency; - Param<string> devicename; END_DECLARE_SIM_OBJECT_PARAMS(BadDevice) BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice) - INIT_PARAM(platform, "Platform"), - INIT_PARAM(mmu, "Memory Controller"), - INIT_PARAM(addr, "Device Address"), - INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams), - INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), - INIT_PARAM(devicename, "Name of device to error on") + INIT_PARAM(devicename, "Name of device to error on"), + INIT_PARAM(pio_addr, "Device Address"), + INIT_PARAM(system, "system object"), + INIT_PARAM(platform, "platform"), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000) END_INIT_SIM_OBJECT_PARAMS(BadDevice) CREATE_SIM_OBJECT(BadDevice) { - return new BadDevice(getInstanceName(), addr, mmu, hier, pio_bus, - devicename); + BadDevice::Params *p = new BadDevice::Params; + p->name =getInstanceName(); + p->platform = platform; + p->pio_addr = pio_addr; + p->pio_delay = pio_latency; + p->system = system; + p->device_name = devicename; + return new BadDevice(p); } REGISTER_SIM_OBJECT("BadDevice", BadDevice) diff --git a/dev/baddev.hh b/dev/baddev.hh index 189f28331..4cf0d6ba4 100644 --- a/dev/baddev.hh +++ b/dev/baddev.hh @@ -37,7 +37,6 @@ #include "base/range.hh" #include "dev/io_device.hh" -class MemoryController; /** * BadDevice @@ -45,51 +44,29 @@ class MemoryController; * the user that the kernel they are running has unsupported * options (i.e. frame buffer) */ -class BadDevice : public PioDevice +class BadDevice : public BasicPioDevice { private: - Addr addr; - static const Addr size = 0xf; - std::string devname; public: + struct Params : public BasicPioDevice::Params + { + std::string device_name; + }; + protected: + const Params *params() const { return (const Params *)_params; } + + public: /** * Constructor for the Baddev Class. - * @param name name of the object + * @param p object parameters * @param a base address of the write - * @param mmu the memory controller - * @param hier object to store parameters universal the device hierarchy - * @param bus The bus that this device is attached to - * @param devicename device that is not implemented - */ - BadDevice(const std::string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *bus, const std::string &devicename); - - /** - * On a read event we just panic aand hopefully print a - * meaningful error message. - * @param req Contains the address to read from. - * @param data A pointer to write the read data to. - * @return The fault condition of the access. - */ - virtual Fault read(MemReqPtr &req, uint8_t *data); - - /** - * On a write event we just panic aand hopefully print a - * meaningful error message. - * @param req Contains the address to write to. - * @param data The data to write. - * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + BadDevice(Params *p); - /** - * Return how long this access will take. - * @param req the memory request to calcuate - * @return Tick when the request is done - */ - Tick cacheAccess(MemReqPtr &req); + virtual Tick read(Packet &pkt); + virtual Tick write(Packet &pkt); }; #endif // __DEV_BADDEV_HH__ diff --git a/dev/io_device.cc b/dev/io_device.cc index 5d3a87006..a2e5a8a0d 100644 --- a/dev/io_device.cc +++ b/dev/io_device.cc @@ -78,7 +78,7 @@ bool PioPort::recvTiming(Packet &pkt) { device->recvAtomic(pkt); - sendTiming(pkt, pkt.time-pkt.req->time); + sendTiming(pkt, pkt.time-pkt.req->getTime()); return Success; } @@ -88,6 +88,22 @@ PioDevice::~PioDevice() delete pioPort; } +void +PioDevice::init() +{ + if (!pioPort) + panic("Pio port not connected to anything!"); + pioPort->sendStatusChange(Port::RangeChange); +} + +void +BasicPioDevice::addressRanges(AddrRangeList &range_list) +{ + assert(pioSize != 0); + range_list.clear(); + range_list.push_back(RangeSize(pioAddr, pioSize)); +} + DmaPort::DmaPort(DmaDevice *dev) : device(dev) @@ -132,7 +148,7 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size, int prevSize = 0; Packet basePkt; - Request baseReq; + Request baseReq(false); basePkt.flags = 0; basePkt.coherence = NULL; @@ -142,8 +158,8 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size, basePkt.cmd = cmd; basePkt.result = Unknown; basePkt.req = NULL; - baseReq.nicReq = true; - baseReq.time = curTick; +// baseReq.nicReq = true; + baseReq.setTime(curTick); completionEvent = event; @@ -154,8 +170,8 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size, pkt->addr = gen.addr(); pkt->size = gen.size(); pkt->req = req; - pkt->req->paddr = pkt->addr; - pkt->req->size = pkt->size; + pkt->req->setPaddr(pkt->addr); + pkt->req->setSize(pkt->size); // Increment the data pointer on a write pkt->data = data ? data + prevSize : NULL ; prevSize += pkt->size; @@ -178,7 +194,7 @@ DmaPort::sendDma(Packet &pkt) transmitList.push_back(&packet); } else if (state == Atomic) {*/ sendAtomic(pkt); - completionEvent->schedule(pkt.time - pkt.req->time); + completionEvent->schedule(pkt.time - pkt.req->getTime()); completionEvent = NULL; /* } else if (state == Functional) { sendFunctional(pkt); diff --git a/dev/io_device.hh b/dev/io_device.hh index a81dae072..5379a664c 100644 --- a/dev/io_device.hh +++ b/dev/io_device.hh @@ -30,7 +30,7 @@ #define __DEV_IO_DEVICE_HH__ #include "base/chunk_generator.hh" -#include "mem/port.hh" +#include "mem/mem_object.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" @@ -172,7 +172,7 @@ class DmaPort : public Port * bother. */ -class PioDevice : public SimObject +class PioDevice : public MemObject { protected: @@ -192,11 +192,17 @@ class PioDevice : public SimObject { return pkt.cmd == Read ? this->read(pkt) : this->write(pkt); } /** Pure virtual function that the device must implement. Called when a read - * command is recieved by the port. */ + * command is recieved by the port. + * @param pkt Packet describing this request + * @return number of ticks it took to complete + */ virtual Tick read(Packet &pkt) = 0; /** Pure virtual function that the device must implement. Called when a - * write command is recieved by the port. */ + * write command is recieved by the port. + * @param pkt Packet describing this request + * @return number of ticks it took to complete + */ virtual Tick write(Packet &pkt) = 0; public: @@ -218,11 +224,14 @@ class PioDevice : public SimObject const Params *params() const { return _params; } PioDevice(Params *p) - : SimObject(params()->name), platform(p->platform), _params(p) + : MemObject(p->name), platform(p->platform), pioPort(NULL), + _params(p) {} virtual ~PioDevice(); + virtual void init(); + virtual Port *getPort(const std::string &if_name) { if (if_name == "pio") { @@ -261,6 +270,11 @@ class BasicPioDevice : public PioDevice : PioDevice(p), pioAddr(p->pio_addr), pioSize(0), pioDelay(p->pio_delay) {} + /** return the address ranges that this device responds to. + * @params range_list range list to populate with ranges + */ + void addressRanges(AddrRangeList &range_list); + }; class DmaDevice : public PioDevice diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc index 7ce43b712..1ed355499 100644 --- a/dev/isa_fake.cc +++ b/dev/isa_fake.cc @@ -34,108 +34,118 @@ #include <string> #include <vector> -#include "arch/alpha/ev5.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" #include "dev/isa_fake.hh" -#include "mem/bus/bus.hh" -#include "mem/bus/pio_interface.hh" -#include "mem/bus/pio_interface_impl.hh" -#include "mem/functional/memory_control.hh" +#include "mem/packet.hh" #include "sim/builder.hh" #include "sim/system.hh" using namespace std; -using namespace TheISA; -IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *pio_bus, Addr size) - : PioDevice(name, NULL), addr(a) +IsaFake::IsaFake(Params *p) + : BasicPioDevice(p) { - mmu->add_child(this, RangeSize(addr, size)); - - if (pio_bus) { - pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, - &IsaFake::cacheAccess); - pioInterface->addAddrRange(RangeSize(addr, size)); - } + pioSize = p->pio_size; } -Fault -IsaFake::read(MemReqPtr &req, uint8_t *data) +Tick +IsaFake::read(Packet &pkt) { - DPRINTF(Tsunami, "read va=%#x size=%d\n", - req->vaddr, req->size); + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); -#if TRACING_ON - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; -#endif + pkt.time = curTick + pioDelay; - switch (req->size) { + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size); + uint8_t *data8; + uint16_t *data16; + uint32_t *data32; + uint64_t *data64; + + switch (pkt.size) { case sizeof(uint64_t): - *(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL; - return NoFault; + if (!pkt.data) { + data64 = new uint64_t; + pkt.data = (uint8_t*)data64; + } else { + data64 = (uint64_t*)pkt.data; + } + *data64 = 0xFFFFFFFFFFFFFFFFULL; + break; case sizeof(uint32_t): - *(uint32_t*)data = 0xFFFFFFFF; - return NoFault; + if (!pkt.data) { + data32 = new uint32_t; + pkt.data = (uint8_t*)data32; + } else { + data32 = (uint32_t*)pkt.data; + } + *data32 = 0xFFFFFFFF; + break; case sizeof(uint16_t): - *(uint16_t*)data = 0xFFFF; - return NoFault; + if (!pkt.data) { + data16 = new uint16_t; + pkt.data = (uint8_t*)data16; + } else { + data16 = (uint16_t*)pkt.data; + } + *data16 = 0xFFFF; + break; case sizeof(uint8_t): - *(uint8_t*)data = 0xFF; - return NoFault; - + if (!pkt.data) { + data8 = new uint8_t; + pkt.data = data8; + } else { + data8 = (uint8_t*)pkt.data; + } + *data8 = 0xFF; + break; default: panic("invalid access size(?) for PCI configspace!\n"); } - DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size); - - return NoFault; -} - -Fault -IsaFake::write(MemReqPtr &req, const uint8_t *data) -{ - DPRINTF(Tsunami, "write - va=%#x size=%d \n", - req->vaddr, req->size); - - //:Addr daddr = (req->paddr & addr_mask) >> 6; - - return NoFault; + pkt.result = Success; + return pioDelay; } Tick -IsaFake::cacheAccess(MemReqPtr &req) +IsaFake::write(Packet &pkt) { - return curTick; + pkt.time = curTick + pioDelay; + DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size); + pkt.result = Success; + return pioDelay; } BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake) - SimObjectParam<MemoryController *> mmu; - Param<Addr> addr; - SimObjectParam<Bus*> pio_bus; + Param<Addr> pio_addr; Param<Tick> pio_latency; - SimObjectParam<HierParams *> hier; - Param<Addr> size; + Param<Addr> pio_size; + SimObjectParam<Platform *> platform; + SimObjectParam<System *> system; END_DECLARE_SIM_OBJECT_PARAMS(IsaFake) BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake) - INIT_PARAM(mmu, "Memory Controller"), - INIT_PARAM(addr, "Device Address"), - INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), - INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams), - INIT_PARAM_DFLT(size, "Size of address range", 0x8) + INIT_PARAM(pio_addr, "Device Address"), + INIT_PARAM(pio_latency, "Programmed IO latency"), + INIT_PARAM(pio_size, "Size of address range"), + INIT_PARAM(platform, "platform"), + INIT_PARAM(system, "system object") END_INIT_SIM_OBJECT_PARAMS(IsaFake) CREATE_SIM_OBJECT(IsaFake) { - return new IsaFake(getInstanceName(), addr, mmu, hier, pio_bus, size); + IsaFake::Params *p = new IsaFake::Params; + p->name = getInstanceName(); + p->pio_addr = pio_addr; + p->pio_delay = pio_latency; + p->pio_size = pio_size; + p->platform = platform; + p->system = system; + return new IsaFake(p); } REGISTER_SIM_OBJECT("IsaFake", IsaFake) diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh index 73e40c681..29050833d 100644 --- a/dev/isa_fake.hh +++ b/dev/isa_fake.hh @@ -37,51 +37,42 @@ #include "base/range.hh" #include "dev/io_device.hh" -class MemoryController; - /** * IsaFake is a device that returns -1 on all reads and * accepts all writes. It is meant to be placed at an address range * so that an mcheck doesn't occur when an os probes a piece of hw * that doesn't exist (e.g. UARTs1-3). */ -class IsaFake : public PioDevice +class IsaFake : public BasicPioDevice { - private: - /** The address in memory that we respond to */ - Addr addr; + public: + struct Params : public BasicPioDevice::Params + { + Addr pio_size; + }; + protected: + const Params *params() const { return (const Params*)_params; } public: /** * The constructor for Tsunmami Fake just registers itself with the MMU. - * @param name name of this device. - * @param a address to respond to. - * @param mmu the mmu we register with. - * @param size number of addresses to respond to + * @param p params structure */ - IsaFake(const std::string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *pio_bus, Addr size = 0x8); + IsaFake(Params *p); /** * This read always returns -1. * @param req The memory request. * @param data Where to put the data. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Tick read(Packet &pkt); /** * All writes are simply ignored. * @param req The memory request. * @param data the data to not write. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); - - /** - * Return how long this access will take. - * @param req the memory request to calcuate - * @return Tick when the request is done - */ - Tick cacheAccess(MemReqPtr &req); + virtual Tick write(Packet &pkt); }; -#endif // __ISA_FAKE_HH__ +#endif // __TSUNAMI_FAKE_HH__ diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 1a138fb39..86a505b9a 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -35,34 +35,25 @@ #include <vector> #include <bitset> -#include "arch/alpha/ev5.hh" #include "base/trace.hh" #include "dev/pciconfigall.hh" -#include "dev/pcidev.hh" +//#include "dev/pcidev.hh" #include "dev/pcireg.h" -#include "mem/bus/bus.hh" -#include "mem/bus/pio_interface.hh" -#include "mem/bus/pio_interface_impl.hh" -#include "mem/functional/memory_control.hh" +#include "dev/platform.hh" +#include "mem/packet.hh" #include "sim/builder.hh" #include "sim/system.hh" using namespace std; -using namespace TheISA; -PciConfigAll::PciConfigAll(const string &name, - Addr a, MemoryController *mmu, - HierParams *hier, Bus *pio_bus, Tick pio_latency) - : PioDevice(name, NULL), addr(a) +PciConfigAll::PciConfigAll(Params *p) + : BasicPioDevice(p) { - mmu->add_child(this, RangeSize(addr, size)); + pioSize = 0xffffff; - if (pio_bus) { - pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, - &PciConfigAll::cacheAccess); - pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * pio_bus->clockRate; - } + // Set backpointer for pci config. Really the config stuff should be able to + // automagically do this + p->platform->pciconfig = this; // Make all the pointers to devices null for(int x=0; x < MAX_PCI_DEV; x++) @@ -77,7 +68,7 @@ PciConfigAll::PciConfigAll(const string &name, void PciConfigAll::startup() { - bitset<256> intLines; +/* bitset<256> intLines; PciDev *tempDev; uint8_t intline; @@ -94,79 +85,109 @@ PciConfigAll::startup() } // devices != NULL } // PCI_FUNC } // PCI_DEV - + */ } -Fault -PciConfigAll::read(MemReqPtr &req, uint8_t *data) +Tick +PciConfigAll::read(Packet &pkt) { + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); - - DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", - req->vaddr, daddr, req->size); - + Addr daddr = pkt.addr - pioAddr; int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; - int reg = daddr & 0xFF; - - if (devices[device][func] == NULL) { - switch (req->size) { - // case sizeof(uint64_t): - // *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF; - // return NoFault; - case sizeof(uint32_t): - *(uint32_t*)data = 0xFFFFFFFF; - return NoFault; - case sizeof(uint16_t): - *(uint16_t*)data = 0xFFFF; - return NoFault; - case sizeof(uint8_t): - *(uint8_t*)data = 0xFF; - return NoFault; - default: - panic("invalid access size(?) for PCI configspace!\n"); - } - } else { - switch (req->size) { - case sizeof(uint32_t): - case sizeof(uint16_t): - case sizeof(uint8_t): - devices[device][func]->readConfig(reg, req->size, data); - return NoFault; - default: - panic("invalid access size(?) for PCI configspace!\n"); - } + //int reg = daddr & 0xFF; + + pkt.time = curTick + pioDelay; + + DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt.addr, daddr, + pkt.size); + + uint8_t *data8; + uint16_t *data16; + uint32_t *data32; + + switch (pkt.size) { +/* case sizeof(uint64_t): + if (!pkt.data) { + data64 = new uint64_t; + pkt.data = (uint8_t*)data64; + } else { + data64 = (uint64_t*)pkt.data; + } + if (devices[device][func] == NULL) + *data64 = 0xFFFFFFFFFFFFFFFFULL; + else + devices[device][func]->readConfig(reg, req.size, data64); + break;*/ + case sizeof(uint32_t): + if (!pkt.data) { + data32 = new uint32_t; + pkt.data = (uint8_t*)data32; + } else { + data32 = (uint32_t*)pkt.data; + } + if (devices[device][func] == NULL) + *data32 = 0xFFFFFFFF; + else + ;//devices[device][func]->readConfig(reg, req.size, data32); + break; + case sizeof(uint16_t): + if (!pkt.data) { + data16 = new uint16_t; + pkt.data = (uint8_t*)data16; + } else { + data16 = (uint16_t*)pkt.data; + } + if (devices[device][func] == NULL) + *data16 = 0xFFFF; + else + ;//devices[device][func]->readConfig(reg, req.size, data16); + break; + case sizeof(uint8_t): + if (!pkt.data) { + data8 = new uint8_t; + pkt.data = data8; + } else { + data8 = (uint8_t*)pkt.data; + } + if (devices[device][func] == NULL) + *data8 = 0xFF; + else + ;//devices[device][func]->readConfig(reg, req.size, data8); + break; + default: + panic("invalid access size(?) for PCI configspace!\n"); } - - DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n", - daddr, req->size); - - return NoFault; + pkt.result = Success; + return pioDelay; } -Fault -PciConfigAll::write(MemReqPtr &req, const uint8_t *data) +Tick +PciConfigAll::write(Packet &pkt) { - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); + pkt.time = curTick + pioDelay; + + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt.size == sizeof(uint8_t) || pkt.size == sizeof(uint16_t) || + pkt.size == sizeof(uint32_t)); + Addr daddr = pkt.addr - pioAddr; int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; - int reg = daddr & 0xFF; +// int reg = daddr & 0xFF; if (devices[device][func] == NULL) panic("Attempting to write to config space on non-existant device\n"); - else if (req->size != sizeof(uint8_t) && - req->size != sizeof(uint16_t) && - req->size != sizeof(uint32_t)) - panic("invalid access size(?) for PCI configspace!\n"); DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n", - req->vaddr, req->size, *(uint32_t*)data); + pkt.addr, pkt.size, *(uint32_t*)pkt.data); - devices[device][func]->writeConfig(reg, req->size, data); +// devices[device][func]->writeConfig(reg, req->size, data); - return NoFault; + return pioDelay; } void @@ -189,40 +210,34 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string §ion) */ } -Tick -PciConfigAll::cacheAccess(MemReqPtr &req) -{ - return curTick + pioLatency; -} - #ifndef DOXYGEN_SHOULD_SKIP_THIS BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll) - SimObjectParam<MemoryController *> mmu; - Param<Addr> addr; - Param<Addr> mask; - SimObjectParam<Bus*> pio_bus; + Param<Addr> pio_addr; Param<Tick> pio_latency; - SimObjectParam<HierParams *> hier; + SimObjectParam<Platform *> platform; + SimObjectParam<System *> system; END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll) BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll) - INIT_PARAM(mmu, "Memory Controller"), - INIT_PARAM(addr, "Device Address"), - INIT_PARAM(mask, "Address Mask"), - INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), - INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) + INIT_PARAM(pio_addr, "Device Address"), + INIT_PARAM(pio_latency, "Programmed IO latency"), + INIT_PARAM(platform, "platform"), + INIT_PARAM(system, "system object") END_INIT_SIM_OBJECT_PARAMS(PciConfigAll) CREATE_SIM_OBJECT(PciConfigAll) { - return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus, - pio_latency); + BasicPioDevice::Params *p = new BasicPioDevice::Params; + p->pio_addr = pio_addr; + p->pio_delay = pio_latency; + p->platform = platform; + p->system = system; + return new PciConfigAll(p); } REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll) diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh index c6a0241d8..b2034594c 100644 --- a/dev/pciconfigall.hh +++ b/dev/pciconfigall.hh @@ -43,7 +43,6 @@ static const uint32_t MAX_PCI_DEV = 32; static const uint32_t MAX_PCI_FUNC = 8; class PciDev; -class MemoryController; /** * PCI Config Space @@ -52,10 +51,9 @@ class MemoryController; * space and passes the requests on to TsunamiPCIDev devices as * appropriate. */ -class PciConfigAll : public PioDevice +class PciConfigAll : public BasicPioDevice { private: - Addr addr; static const Addr size = 0xffffff; /** @@ -67,15 +65,9 @@ class PciConfigAll : public PioDevice public: /** * Constructor for PCIConfigAll - * @param name name of the object - * @param a base address of the write - * @param mmu the memory controller - * @param hier object to store parameters universal the device hierarchy - * @param bus The bus that this device is attached to + * @param p parameters structure */ - PciConfigAll(const std::string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *pio_bus, Tick pio_latency); - + PciConfigAll(Params *p); /** * Check if a device exists. @@ -99,11 +91,10 @@ class PciConfigAll : public PioDevice * Read something in PCI config space. If the device does not exist * -1 is returned, if the device does exist its PciDev::ReadConfig (or the * virtual function that overrides) it is called. - * @param req Contains the address of the field to read. - * @param data Return the field read. - * @return The fault condition of the access. + * @param pkt Contains the address of the field to read. + * @return Amount of time to do the read */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Tick read(Packet &pkt); /** * Write to PCI config spcae. If the device does not exit the simulator @@ -114,7 +105,7 @@ class PciConfigAll : public PioDevice * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Tick write(Packet &pkt); /** * Start up function to check if more than one person is using an interrupt line @@ -134,14 +125,6 @@ class PciConfigAll : public PioDevice * @param section The section name of this object */ virtual void unserialize(Checkpoint *cp, const std::string §ion); - - /** - * Return how long this access will take. - * @param req the memory request to calcuate - * @return Tick when the request is done - */ - Tick cacheAccess(MemReqPtr &req); - }; #endif // __PCICONFIGALL_HH__ diff --git a/dev/platform.cc b/dev/platform.cc index 5b667b12c..9d10e0828 100644 --- a/dev/platform.cc +++ b/dev/platform.cc @@ -33,8 +33,8 @@ using namespace std; using namespace TheISA; -Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci) - : SimObject(name), intrctrl(intctrl), pciconfig(pci) +Platform::Platform(const string &name, IntrControl *intctrl) + : SimObject(name), intrctrl(intctrl) { } diff --git a/dev/platform.hh b/dev/platform.hh index 2c37048d4..f149ca2fb 100644 --- a/dev/platform.hh +++ b/dev/platform.hh @@ -59,8 +59,9 @@ class Platform : public SimObject System *system; public: - Platform(const std::string &name, IntrControl *intctrl, PciConfigAll *pci); + Platform(const std::string &name, IntrControl *intctrl); virtual ~Platform(); + virtual void init() { if (pciconfig == NULL) panic("PCI Config not set"); } virtual void postConsoleInt() = 0; virtual void clearConsoleInt() = 0; virtual Tick intrFrequency() = 0; diff --git a/dev/tsunami.cc b/dev/tsunami.cc index 58fc7434e..ed011531d 100644 --- a/dev/tsunami.cc +++ b/dev/tsunami.cc @@ -36,12 +36,10 @@ #include "cpu/intr_control.hh" #include "dev/simconsole.hh" -#include "dev/ide_ctrl.hh" #include "dev/tsunami_cchip.hh" #include "dev/tsunami_pchip.hh" #include "dev/tsunami_io.hh" #include "dev/tsunami.hh" -#include "dev/pciconfigall.hh" #include "sim/builder.hh" #include "sim/system.hh" @@ -49,9 +47,8 @@ using namespace std; //Should this be AlphaISA? using namespace TheISA; -Tsunami::Tsunami(const string &name, System *s, IntrControl *ic, - PciConfigAll *pci) - : Platform(name, ic, pci), system(s) +Tsunami::Tsunami(const string &name, System *s, IntrControl *ic) + : Platform(name, ic), system(s) { // set the back pointer from the system to myself system->platform = this; @@ -112,21 +109,19 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami) SimObjectParam<System *> system; SimObjectParam<IntrControl *> intrctrl; - SimObjectParam<PciConfigAll *> pciconfig; END_DECLARE_SIM_OBJECT_PARAMS(Tsunami) BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami) INIT_PARAM(system, "system"), - INIT_PARAM(intrctrl, "interrupt controller"), - INIT_PARAM(pciconfig, "PCI configuration") + INIT_PARAM(intrctrl, "interrupt controller") END_INIT_SIM_OBJECT_PARAMS(Tsunami) CREATE_SIM_OBJECT(Tsunami) { - return new Tsunami(getInstanceName(), system, intrctrl, pciconfig); + return new Tsunami(getInstanceName(), system, intrctrl); } REGISTER_SIM_OBJECT("Tsunami", Tsunami) diff --git a/dev/tsunami.hh b/dev/tsunami.hh index 7fd91d5b2..668c82674 100644 --- a/dev/tsunami.hh +++ b/dev/tsunami.hh @@ -38,12 +38,9 @@ #include "dev/platform.hh" class IdeController; -class TlaserClock; -class NSGigE; class TsunamiCChip; class TsunamiPChip; class TsunamiIO; -class PciConfigAll; class System; /** @@ -86,8 +83,7 @@ class Tsunami : public Platform * @param name name of the object * @param intrctrl pointer to the interrupt controller */ - Tsunami(const std::string &name, System *s, IntrControl *intctrl, - PciConfigAll *pci); + Tsunami(const std::string &name, System *s, IntrControl *intctrl); /** * Return the interrupting frequency to AlphaAccess diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 8c6db8a43..81ad9a71d 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -39,10 +39,7 @@ #include "dev/tsunami_cchip.hh" #include "dev/tsunamireg.h" #include "dev/tsunami.hh" -#include "mem/bus/bus.hh" -#include "mem/bus/pio_interface.hh" -#include "mem/bus/pio_interface_impl.hh" -#include "mem/functional/memory_control.hh" +#include "mem/port.hh" #include "cpu/exec_context.hh" #include "cpu/intr_control.hh" #include "sim/builder.hh" @@ -52,19 +49,10 @@ using namespace std; //Should this be AlphaISA? using namespace TheISA; -TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, - Bus* pio_bus, Tick pio_latency) - : PioDevice(name, t), addr(a), tsunami(t) +TsunamiCChip::TsunamiCChip(Params *p) + : BasicPioDevice(p), tsunami(p->tsunami) { - mmu->add_child(this, RangeSize(addr, size)); - - if (pio_bus) { - pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, - &TsunamiCChip::cacheAccess); - pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * pio_bus->clockRate; - } + pioSize = 0xfffffff; drir = 0; ipint = 0; @@ -80,315 +68,310 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, tsunami->cchip = this; } -Fault -TsunamiCChip::read(MemReqPtr &req, uint8_t *data) +Tick +TsunamiCChip::read(Packet &pkt) { - DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size); - Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - ExecContext *xc = req->xc; + pkt.time = curTick + pioDelay; + Addr regnum = (pkt.addr - pioAddr) >> 6; + Addr daddr = (pkt.addr - pioAddr); - switch (req->size) { + uint64_t *data64; + + switch (pkt.size) { case sizeof(uint64_t): + if (!pkt.data) { + data64 = new uint64_t; + pkt.data = (uint8_t*)data64; + } else + data64 = (uint64_t*)pkt.data; + if (daddr & TSDEV_CC_BDIMS) { - *(uint64_t*)data = dim[(daddr >> 4) & 0x3F]; - return NoFault; + *data64 = dim[(daddr >> 4) & 0x3F]; + break; } if (daddr & TSDEV_CC_BDIRS) { - *(uint64_t*)data = dir[(daddr >> 4) & 0x3F]; - return NoFault; + *data64 = dir[(daddr >> 4) & 0x3F]; + break; } switch(regnum) { case TSDEV_CC_CSR: - *(uint64_t*)data = 0x0; - return NoFault; + *data64 = 0x0; + break; case TSDEV_CC_MTR: panic("TSDEV_CC_MTR not implemeted\n"); - return NoFault; + break; case TSDEV_CC_MISC: - *(uint64_t*)data = (ipint << 8) & 0xF | - (itint << 4) & 0xF | - (xc->readCpuId() & 0x3); - return NoFault; + *data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF | + (pkt.req->getCpuNum() & 0x3); + break; case TSDEV_CC_AAR0: case TSDEV_CC_AAR1: case TSDEV_CC_AAR2: case TSDEV_CC_AAR3: - *(uint64_t*)data = 0; - return NoFault; + *data64 = 0; + break; case TSDEV_CC_DIM0: - *(uint64_t*)data = dim[0]; - return NoFault; + *data64 = dim[0]; + break; case TSDEV_CC_DIM1: - *(uint64_t*)data = dim[1]; - return NoFault; + *data64 = dim[1]; + break; case TSDEV_CC_DIM2: - *(uint64_t*)data = dim[2]; - return NoFault; + *data64 = dim[2]; + break; case TSDEV_CC_DIM3: - *(uint64_t*)data = dim[3]; - return NoFault; + *data64 = dim[3]; + break; case TSDEV_CC_DIR0: - *(uint64_t*)data = dir[0]; - return NoFault; + *data64 = dir[0]; + break; case TSDEV_CC_DIR1: - *(uint64_t*)data = dir[1]; - return NoFault; + *data64 = dir[1]; + break; case TSDEV_CC_DIR2: - *(uint64_t*)data = dir[2]; - return NoFault; + *data64 = dir[2]; + break; case TSDEV_CC_DIR3: - *(uint64_t*)data = dir[3]; - return NoFault; + *data64 = dir[3]; + break; case TSDEV_CC_DRIR: - *(uint64_t*)data = drir; - return NoFault; + *data64 = drir; + break; case TSDEV_CC_PRBEN: panic("TSDEV_CC_PRBEN not implemented\n"); - return NoFault; + break; case TSDEV_CC_IIC0: case TSDEV_CC_IIC1: case TSDEV_CC_IIC2: case TSDEV_CC_IIC3: panic("TSDEV_CC_IICx not implemented\n"); - return NoFault; + break; case TSDEV_CC_MPR0: case TSDEV_CC_MPR1: case TSDEV_CC_MPR2: case TSDEV_CC_MPR3: panic("TSDEV_CC_MPRx not implemented\n"); - return NoFault; + break; case TSDEV_CC_IPIR: - *(uint64_t*)data = ipint; - return NoFault; + *data64 = ipint; + break; case TSDEV_CC_ITIR: - *(uint64_t*)data = itint; - return NoFault; + *data64 = itint; + break; default: panic("default in cchip read reached, accessing 0x%x\n"); } // uint64_t break; case sizeof(uint32_t): - if (regnum == TSDEV_CC_DRIR) { - warn("accessing DRIR with 32 bit read, " - "hopefully your just reading this for timing"); - *(uint32_t*)data = drir; - } else - panic("invalid access size(?) for tsunami register!\n"); - return NoFault; case sizeof(uint16_t): case sizeof(uint8_t): default: panic("invalid access size(?) for tsunami register!\n"); } - DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size); + DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", + regnum, pkt.size, *data64); - return NoFault; + pkt.result = Success; + return pioDelay; } -Fault -TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) +Tick +TsunamiCChip::write(Packet &pkt) { - DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n", - req->vaddr, *(uint64_t*)data, req->size); + pkt.time = curTick + pioDelay; - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); - Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; - bool supportedWrite = false; + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + Addr daddr = pkt.addr - pioAddr; + Addr regnum = (pkt.addr - pioAddr) >> 6 ; - switch (req->size) { - case sizeof(uint64_t): - if (daddr & TSDEV_CC_BDIMS) - { - int number = (daddr >> 4) & 0x3F; - - uint64_t bitvector; - uint64_t olddim; - uint64_t olddir; - - olddim = dim[number]; - olddir = dir[number]; - dim[number] = *(uint64_t*)data; - dir[number] = dim[number] & drir; - for(int x = 0; x < Tsunami::Max_CPUs; x++) - { - bitvector = ULL(1) << x; - // Figure out which bits have changed - if ((dim[number] & bitvector) != (olddim & bitvector)) - { - // The bit is now set and it wasn't before (set) - if((dim[number] & bitvector) && (dir[number] & bitvector)) - { - tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in posting dir" - " interrupt to cpu %d\n", number); - } - else if ((olddir & bitvector) && - !(dir[number] & bitvector)) - { - // The bit was set and now its now clear and - // we were interrupting on that bit before - tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in clear" - " dir interrupt to cpu %d\n", number); + uint64_t val = *(uint64_t *)pkt.data; + assert(pkt.size == sizeof(uint64_t)); - } + DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, val); + bool supportedWrite = false; - } - } - return NoFault; - } - switch(regnum) { - case TSDEV_CC_CSR: - panic("TSDEV_CC_CSR write\n"); - return NoFault; - case TSDEV_CC_MTR: - panic("TSDEV_CC_MTR write not implemented\n"); - return NoFault; - case TSDEV_CC_MISC: - uint64_t ipreq; - ipreq = (*(uint64_t*)data >> 12) & 0xF; - //If it is bit 12-15, this is an IPI post - if (ipreq) { - reqIPI(ipreq); - supportedWrite = true; + if (daddr & TSDEV_CC_BDIMS) + { + int number = (daddr >> 4) & 0x3F; + + uint64_t bitvector; + uint64_t olddim; + uint64_t olddir; + + olddim = dim[number]; + olddir = dir[number]; + dim[number] = val; + dir[number] = dim[number] & drir; + for(int x = 0; x < Tsunami::Max_CPUs; x++) + { + bitvector = ULL(1) << x; + // Figure out which bits have changed + if ((dim[number] & bitvector) != (olddim & bitvector)) + { + // The bit is now set and it wasn't before (set) + if((dim[number] & bitvector) && (dir[number] & bitvector)) + { + tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); + DPRINTF(Tsunami, "dim write resulting in posting dir" + " interrupt to cpu %d\n", number); } + else if ((olddir & bitvector) && + !(dir[number] & bitvector)) + { + // The bit was set and now its now clear and + // we were interrupting on that bit before + tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); + DPRINTF(Tsunami, "dim write resulting in clear" + " dir interrupt to cpu %d\n", number); - //If it is bit 8-11, this is an IPI clear - uint64_t ipintr; - ipintr = (*(uint64_t*)data >> 8) & 0xF; - if (ipintr) { - clearIPI(ipintr); - supportedWrite = true; } - //If it is the 4-7th bit, clear the RTC interrupt - uint64_t itintr; - itintr = (*(uint64_t*)data >> 4) & 0xF; - if (itintr) { - clearITI(itintr); - supportedWrite = true; - } - // ignore NXMs - if (*(uint64_t*)data & 0x10000000) - supportedWrite = true; + } + } + } else { + switch(regnum) { + case TSDEV_CC_CSR: + panic("TSDEV_CC_CSR write\n"); + case TSDEV_CC_MTR: + panic("TSDEV_CC_MTR write not implemented\n"); + case TSDEV_CC_MISC: + uint64_t ipreq; + ipreq = (val >> 12) & 0xF; + //If it is bit 12-15, this is an IPI post + if (ipreq) { + reqIPI(ipreq); + supportedWrite = true; + } - if(!supportedWrite) - panic("TSDEV_CC_MISC write not implemented\n"); + //If it is bit 8-11, this is an IPI clear + uint64_t ipintr; + ipintr = (val >> 8) & 0xF; + if (ipintr) { + clearIPI(ipintr); + supportedWrite = true; + } - return NoFault; - case TSDEV_CC_AAR0: - case TSDEV_CC_AAR1: - case TSDEV_CC_AAR2: - case TSDEV_CC_AAR3: - panic("TSDEV_CC_AARx write not implemeted\n"); - return NoFault; - case TSDEV_CC_DIM0: - case TSDEV_CC_DIM1: - case TSDEV_CC_DIM2: - case TSDEV_CC_DIM3: - int number; - if(regnum == TSDEV_CC_DIM0) - number = 0; - else if(regnum == TSDEV_CC_DIM1) - number = 1; - else if(regnum == TSDEV_CC_DIM2) - number = 2; - else - number = 3; - - uint64_t bitvector; - uint64_t olddim; - uint64_t olddir; - - olddim = dim[number]; - olddir = dir[number]; - dim[number] = *(uint64_t*)data; - dir[number] = dim[number] & drir; - for(int x = 0; x < 64; x++) - { - bitvector = ULL(1) << x; - // Figure out which bits have changed - if ((dim[number] & bitvector) != (olddim & bitvector)) - { - // The bit is now set and it wasn't before (set) - if((dim[number] & bitvector) && (dir[number] & bitvector)) - { - tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); - } - else if ((olddir & bitvector) && - !(dir[number] & bitvector)) - { - // The bit was set and now its now clear and - // we were interrupting on that bit before - tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in clear" - " dir interrupt to cpu %d\n", - x); - - } - - - } - } - return NoFault; - case TSDEV_CC_DIR0: - case TSDEV_CC_DIR1: - case TSDEV_CC_DIR2: - case TSDEV_CC_DIR3: - panic("TSDEV_CC_DIR write not implemented\n"); - case TSDEV_CC_DRIR: - panic("TSDEV_CC_DRIR write not implemented\n"); - case TSDEV_CC_PRBEN: - panic("TSDEV_CC_PRBEN write not implemented\n"); - case TSDEV_CC_IIC0: - case TSDEV_CC_IIC1: - case TSDEV_CC_IIC2: - case TSDEV_CC_IIC3: - panic("TSDEV_CC_IICx write not implemented\n"); - case TSDEV_CC_MPR0: - case TSDEV_CC_MPR1: - case TSDEV_CC_MPR2: - case TSDEV_CC_MPR3: - panic("TSDEV_CC_MPRx write not implemented\n"); - case TSDEV_CC_IPIR: - clearIPI(*(uint64_t*)data); - return NoFault; - case TSDEV_CC_ITIR: - clearITI(*(uint64_t*)data); - return NoFault; - case TSDEV_CC_IPIQ: - reqIPI(*(uint64_t*)data); - return NoFault; - default: - panic("default in cchip read reached, accessing 0x%x\n"); - } + //If it is the 4-7th bit, clear the RTC interrupt + uint64_t itintr; + itintr = (val >> 4) & 0xF; + if (itintr) { + clearITI(itintr); + supportedWrite = true; + } - break; - case sizeof(uint32_t): - case sizeof(uint16_t): - case sizeof(uint8_t): - default: - panic("invalid access size(?) for tsunami register!\n"); - } + // ignore NXMs + if (val & 0x10000000) + supportedWrite = true; + + if(!supportedWrite) + panic("TSDEV_CC_MISC write not implemented\n"); + + break; + case TSDEV_CC_AAR0: + case TSDEV_CC_AAR1: + case TSDEV_CC_AAR2: + case TSDEV_CC_AAR3: + panic("TSDEV_CC_AARx write not implemeted\n"); + case TSDEV_CC_DIM0: + case TSDEV_CC_DIM1: + case TSDEV_CC_DIM2: + case TSDEV_CC_DIM3: + int number; + if(regnum == TSDEV_CC_DIM0) + number = 0; + else if(regnum == TSDEV_CC_DIM1) + number = 1; + else if(regnum == TSDEV_CC_DIM2) + number = 2; + else + number = 3; + + uint64_t bitvector; + uint64_t olddim; + uint64_t olddir; + + olddim = dim[number]; + olddir = dir[number]; + dim[number] = val; + dir[number] = dim[number] & drir; + for(int x = 0; x < 64; x++) + { + bitvector = ULL(1) << x; + // Figure out which bits have changed + if ((dim[number] & bitvector) != (olddim & bitvector)) + { + // The bit is now set and it wasn't before (set) + if((dim[number] & bitvector) && (dir[number] & bitvector)) + { + tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); + DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); + } + else if ((olddir & bitvector) && + !(dir[number] & bitvector)) + { + // The bit was set and now its now clear and + // we were interrupting on that bit before + tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); + DPRINTF(Tsunami, "dim write resulting in clear" + " dir interrupt to cpu %d\n", + x); - DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); + } - return NoFault; + + } + } + break; + case TSDEV_CC_DIR0: + case TSDEV_CC_DIR1: + case TSDEV_CC_DIR2: + case TSDEV_CC_DIR3: + panic("TSDEV_CC_DIR write not implemented\n"); + case TSDEV_CC_DRIR: + panic("TSDEV_CC_DRIR write not implemented\n"); + case TSDEV_CC_PRBEN: + panic("TSDEV_CC_PRBEN write not implemented\n"); + case TSDEV_CC_IIC0: + case TSDEV_CC_IIC1: + case TSDEV_CC_IIC2: + case TSDEV_CC_IIC3: + panic("TSDEV_CC_IICx write not implemented\n"); + case TSDEV_CC_MPR0: + case TSDEV_CC_MPR1: + case TSDEV_CC_MPR2: + case TSDEV_CC_MPR3: + panic("TSDEV_CC_MPRx write not implemented\n"); + case TSDEV_CC_IPIR: + clearIPI(val); + break; + case TSDEV_CC_ITIR: + clearITI(val); + break; + case TSDEV_CC_IPIQ: + reqIPI(val); + break; + default: + panic("default in cchip read reached, accessing 0x%x\n"); + } // swtich(regnum) + } // not BIG_TSUNAMI write + pkt.result = Success; + return pioDelay; } void @@ -472,11 +455,11 @@ TsunamiCChip::postRTC() for (int i = 0; i < size; i++) { uint64_t cpumask = ULL(1) << i; - if (!(cpumask & itint)) { - itint |= cpumask; - tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); - DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i); - } + if (!(cpumask & itint)) { + itint |= cpumask; + tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); + DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i); + } } } @@ -491,11 +474,11 @@ TsunamiCChip::postDRIR(uint32_t interrupt) for(int i=0; i < size; i++) { dir[i] = dim[i] & drir; - if (dim[i] & bitvector) { - tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); - DPRINTF(Tsunami, "posting dir interrupt to cpu %d," + if (dim[i] & bitvector) { + tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); + DPRINTF(Tsunami, "posting dir interrupt to cpu %d," "interrupt %d\n",i, interrupt); - } + } } } @@ -510,25 +493,19 @@ TsunamiCChip::clearDRIR(uint32_t interrupt) { drir &= ~bitvector; for(int i=0; i < size; i++) { - if (dir[i] & bitvector) { - tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); - DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," + if (dir[i] & bitvector) { + tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); + DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," "interrupt %d\n",i, interrupt); - } - dir[i] = dim[i] & drir; + } + dir[i] = dim[i] & drir; } } else DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); } -Tick -TsunamiCChip::cacheAccess(MemReqPtr &req) -{ - return curTick + pioLatency; -} - void TsunamiCChip::serialize(std::ostream &os) @@ -552,30 +529,34 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) - SimObjectParam<Tsunami *> tsunami; - SimObjectParam<MemoryController *> mmu; - Param<Addr> addr; - SimObjectParam<Bus*> pio_bus; + Param<Addr> pio_addr; Param<Tick> pio_latency; - SimObjectParam<HierParams *> hier; + SimObjectParam<Platform *> platform; + SimObjectParam<System *> system; + SimObjectParam<Tsunami *> tsunami; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) - INIT_PARAM(tsunami, "Tsunami"), - INIT_PARAM(mmu, "Memory Controller"), - INIT_PARAM(addr, "Device Address"), - INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), - INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) + INIT_PARAM(pio_addr, "Device Address"), + INIT_PARAM(pio_latency, "Programmed IO latency"), + INIT_PARAM(platform, "platform"), + INIT_PARAM(system, "system object"), + INIT_PARAM(tsunami, "Tsunami") END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) CREATE_SIM_OBJECT(TsunamiCChip) { - return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, - pio_bus, pio_latency); + TsunamiCChip::Params *p = new TsunamiCChip::Params; + p->name = getInstanceName(); + p->pio_addr = pio_addr; + p->pio_delay = pio_latency; + p->platform = platform; + p->system = system; + p->tsunami = tsunami; + return new TsunamiCChip(p); } REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh index d88ad375f..6cd6cf13f 100644 --- a/dev/tsunami_cchip.hh +++ b/dev/tsunami_cchip.hh @@ -37,21 +37,13 @@ #include "base/range.hh" #include "dev/io_device.hh" -class MemoryController; /** * Tsunami CChip CSR Emulation. This device includes all the interrupt * handling code for the chipset. */ -class TsunamiCChip : public PioDevice +class TsunamiCChip : public BasicPioDevice { - private: - /** The base address of this device */ - Addr addr; - - /** The size of mappad from the above address */ - static const Addr size = 0xfffffff; - protected: /** * pointer to the tsunami object. @@ -85,36 +77,24 @@ class TsunamiCChip : public PioDevice uint64_t itint; public: + struct Params : public BasicPioDevice::Params + { + Tsunami *tsunami; + }; + protected: + const Params *params() const {return (const Params *)_params; } + + public: /** * Initialize the Tsunami CChip by setting all of the * device register to 0. - * @param name name of this device. - * @param t pointer back to the Tsunami object that we belong to. - * @param a address we are mapped at. - * @param mmu pointer to the memory controller that sends us events. - * @param hier object to store parameters universal the device hierarchy - * @param bus The bus that this device is attached to + * @param p params struct */ - TsunamiCChip(const std::string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, Bus *pio_bus, - Tick pio_latency); - - /** - * Process a read to the CChip. - * @param req Contains the address to read from. - * @param data A pointer to write the read data to. - * @return The fault condition of the access. - */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + TsunamiCChip(Params *p); + virtual Tick read(Packet &pkt); - /** - * Process a write to the CChip. - * @param req Contains the address to write to. - * @param data The data to write. - * @return The fault condition of the access. - */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Tick write(Packet &pkt); /** * post an RTC interrupt to the CPU @@ -165,12 +145,6 @@ class TsunamiCChip : public PioDevice */ virtual void unserialize(Checkpoint *cp, const std::string §ion); - /** - * Return how long this access will take. - * @param req the memory request to calcuate - * @return Tick when the request is done - */ - Tick cacheAccess(MemReqPtr &req); }; #endif // __TSUNAMI_CCHIP_HH__ diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 14fa97341..ebf3492ac 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -36,19 +36,16 @@ #include <string> #include <vector> -#include "arch/alpha/ev5.hh" #include "base/trace.hh" -#include "dev/tsunami_io.hh" -#include "dev/tsunami.hh" #include "dev/pitreg.h" -#include "mem/bus/bus.hh" -#include "mem/bus/pio_interface.hh" -#include "mem/bus/pio_interface_impl.hh" -#include "sim/builder.hh" +#include "dev/rtcreg.h" #include "dev/tsunami_cchip.hh" +#include "dev/tsunami.hh" +#include "dev/tsunami_io.hh" #include "dev/tsunamireg.h" -#include "dev/rtcreg.h" -#include "mem/functional/memory_control.hh" +#include "mem/port.hh" +#include "sim/builder.hh" +#include "sim/system.hh" using namespace std; //Should this be AlphaISA? @@ -80,38 +77,38 @@ TsunamiIO::RTC::set_time(time_t t) } void -TsunamiIO::RTC::writeAddr(const uint8_t *data) +TsunamiIO::RTC::writeAddr(const uint8_t data) { - if (*data <= RTC_STAT_REGD) - addr = *data; + if (data <= RTC_STAT_REGD) + addr = data; else panic("RTC addresses over 0xD are not implemented.\n"); } void -TsunamiIO::RTC::writeData(const uint8_t *data) +TsunamiIO::RTC::writeData(const uint8_t data) { if (addr < RTC_STAT_REGA) - clock_data[addr] = *data; + clock_data[addr] = data; else { switch (addr) { case RTC_STAT_REGA: - if (*data != (RTCA_32768HZ | RTCA_1024HZ)) + if (data != (RTCA_32768HZ | RTCA_1024HZ)) panic("Unimplemented RTC register A value write!\n"); - stat_regA = *data; + stat_regA = data; break; case RTC_STAT_REGB: - if ((*data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR)) + if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR)) panic("Write to RTC reg B bits that are not implemented!\n"); - if (*data & RTCB_PRDC_IE) { + if (data & RTCB_PRDC_IE) { if (!event.scheduled()) event.scheduleIntr(); } else { if (event.scheduled()) event.deschedule(); } - stat_regB = *data; + stat_regB = data; break; case RTC_STAT_REGC: case RTC_STAT_REGD: @@ -207,24 +204,24 @@ TsunamiIO::PITimer::PITimer(const string &name) } void -TsunamiIO::PITimer::writeControl(const uint8_t *data) +TsunamiIO::PITimer::writeControl(const uint8_t data) { int rw; int sel; - sel = GET_CTRL_SEL(*data); + sel = GET_CTRL_SEL(data); if (sel == PIT_READ_BACK) panic("PITimer Read-Back Command is not implemented.\n"); - rw = GET_CTRL_RW(*data); + rw = GET_CTRL_RW(data); if (rw == PIT_RW_LATCH_COMMAND) counter[sel]->latchCount(); else { counter[sel]->setRW(rw); - counter[sel]->setMode(GET_CTRL_MODE(*data)); - counter[sel]->setBCD(GET_CTRL_BCD(*data)); + counter[sel]->setMode(GET_CTRL_MODE(data)); + counter[sel]->setBCD(GET_CTRL_BCD(data)); } } @@ -296,11 +293,11 @@ TsunamiIO::PITimer::Counter::read(uint8_t *data) } void -TsunamiIO::PITimer::Counter::write(const uint8_t *data) +TsunamiIO::PITimer::Counter::write(const uint8_t data) { switch (write_byte) { case LSB: - count = (count & 0xFF00) | *data; + count = (count & 0xFF00) | data; if (event.scheduled()) event.deschedule(); @@ -309,7 +306,7 @@ TsunamiIO::PITimer::Counter::write(const uint8_t *data) break; case MSB: - count = (count & 0x00FF) | (*data << 8); + count = (count & 0x00FF) | (data << 8); period = count; if (period > 0) { @@ -417,26 +414,17 @@ TsunamiIO::PITimer::Counter::CounterEvent::description() return "tsunami 8254 Interval timer"; } -TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time, - Addr a, MemoryController *mmu, HierParams *hier, - Bus *pio_bus, Tick pio_latency, Tick ci) - : PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t), - pitimer(name + "pitimer"), rtc(name + ".rtc", t, ci) +TsunamiIO::TsunamiIO(Params *p) + : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"), + rtc(p->name + ".rtc", p->tsunami, p->frequency) { - mmu->add_child(this, RangeSize(addr, size)); - - if (pio_bus) { - pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, - &TsunamiIO::cacheAccess); - pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * pio_bus->clockRate; - } + pioSize = 0xff; // set the back pointer from tsunami to myself tsunami->io = this; timerData = 0; - rtc.set_time(init_time == 0 ? time(NULL) : init_time); + rtc.set_time(p->init_time == 0 ? time(NULL) : p->init_time); picr = 0; picInterrupting = false; } @@ -444,185 +432,175 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time, Tick TsunamiIO::frequency() const { - return Clock::Frequency / clockInterval; + return Clock::Frequency / params()->frequency; } -Fault -TsunamiIO::read(MemReqPtr &req, uint8_t *data) +Tick +TsunamiIO::read(Packet &pkt) { - DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", - req->vaddr, req->size, req->vaddr & 0xfff); + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + + pkt.time = curTick + pioDelay; + Addr daddr = pkt.addr - pioAddr; + + DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt.addr, + pkt.size, daddr); - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); + uint8_t *data8; + uint64_t *data64; - switch(req->size) { - case sizeof(uint8_t): + if (pkt.size == sizeof(uint8_t)) { + + if (!pkt.data) { + data8 = new uint8_t; + pkt.data = data8; + } else + data8 = pkt.data; switch(daddr) { // PIC1 mask read case TSDEV_PIC1_MASK: - *(uint8_t*)data = ~mask1; - return NoFault; + *data8 = ~mask1; + break; case TSDEV_PIC2_MASK: - *(uint8_t*)data = ~mask2; - return NoFault; + *data8 = ~mask2; + break; case TSDEV_PIC1_ISR: // !!! If this is modified 64bit case needs to be too // Pal code has to do a 64 bit physical read because there is // no load physical byte instruction - *(uint8_t*)data = picr; - return NoFault; + *data8 = picr; + break; case TSDEV_PIC2_ISR: // PIC2 not implemnted... just return 0 - *(uint8_t*)data = 0x00; - return NoFault; + *data8 = 0x00; + break; case TSDEV_TMR0_DATA: - pitimer.counter0.read(data); - return NoFault; + pitimer.counter0.read(data8); + break; case TSDEV_TMR1_DATA: - pitimer.counter1.read(data); - return NoFault; + pitimer.counter1.read(data8); + break; case TSDEV_TMR2_DATA: - pitimer.counter2.read(data); - return NoFault; + pitimer.counter2.read(data8); + break; case TSDEV_RTC_DATA: - rtc.readData(data); - return NoFault; + rtc.readData(data8); + break; case TSDEV_CTRL_PORTB: if (pitimer.counter2.outputHigh()) - *data = PORTB_SPKR_HIGH; + *data8 = PORTB_SPKR_HIGH; else - *data = 0x00; - return NoFault; + *data8 = 0x00; + break; default: - panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); + panic("I/O Read - va%#x size %d\n", pkt.addr, pkt.size); } - case sizeof(uint16_t): - case sizeof(uint32_t): - panic("I/O Read - invalid size - va %#x size %d\n", - req->vaddr, req->size); - - case sizeof(uint64_t): - switch(daddr) { - case TSDEV_PIC1_ISR: - // !!! If this is modified 8bit case needs to be too - // Pal code has to do a 64 bit physical read because there is - // no load physical byte instruction - *(uint64_t*)data = (uint64_t)picr; - return NoFault; - default: - panic("I/O Read - invalid size - va %#x size %d\n", - req->vaddr, req->size); - } - - default: - panic("I/O Read - invalid size - va %#x size %d\n", - req->vaddr, req->size); + } else if (pkt.size == sizeof(uint64_t)) { + if (!pkt.data) { + data64 = new uint64_t; + pkt.data = (uint8_t*)data64; + } else + data64 = (uint64_t*)pkt.data; + + if (daddr == TSDEV_PIC1_ISR) + *data64 = picr; + else + panic("I/O Read - invalid addr - va %#x size %d\n", + pkt.addr, pkt.size); + } else { + panic("I/O Read - invalid size - va %#x size %d\n", pkt.addr, pkt.size); } - panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); - - return NoFault; + pkt.result = Success; + return pioDelay; } -Fault -TsunamiIO::write(MemReqPtr &req, const uint8_t *data) +Tick +TsunamiIO::write(Packet &pkt) { + pkt.time = curTick + pioDelay; + + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + Addr daddr = pkt.addr - pioAddr; + uint8_t val = *pkt.data; #if TRACING_ON - uint8_t dt = *(uint8_t*)data; - uint64_t dt64 = dt; + uint64_t dt64 = val; #endif DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", - req->vaddr, req->size, req->vaddr & 0xfff, dt64); + pkt.addr, pkt.size, pkt.addr & 0xfff, dt64); - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); + assert(pkt.size == sizeof(uint8_t)); - switch(req->size) { - case sizeof(uint8_t): - switch(daddr) { - case TSDEV_PIC1_MASK: - mask1 = ~(*(uint8_t*)data); - if ((picr & mask1) && !picInterrupting) { - picInterrupting = true; - tsunami->cchip->postDRIR(55); - DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); - } - if ((!(picr & mask1)) && picInterrupting) { - picInterrupting = false; - tsunami->cchip->clearDRIR(55); - DPRINTF(Tsunami, "clearing pic interrupt\n"); - } - return NoFault; - case TSDEV_PIC2_MASK: - mask2 = *(uint8_t*)data; - //PIC2 Not implemented to interrupt - return NoFault; - case TSDEV_PIC1_ACK: - // clear the interrupt on the PIC - picr &= ~(1 << (*(uint8_t*)data & 0xF)); - if (!(picr & mask1)) - tsunami->cchip->clearDRIR(55); - return NoFault; - case TSDEV_DMA1_CMND: - return NoFault; - case TSDEV_DMA2_CMND: - return NoFault; - case TSDEV_DMA1_MMASK: - return NoFault; - case TSDEV_DMA2_MMASK: - return NoFault; - case TSDEV_PIC2_ACK: - return NoFault; - case TSDEV_DMA1_RESET: - return NoFault; - case TSDEV_DMA2_RESET: - return NoFault; - case TSDEV_DMA1_MODE: - mode1 = *(uint8_t*)data; - return NoFault; - case TSDEV_DMA2_MODE: - mode2 = *(uint8_t*)data; - return NoFault; - case TSDEV_DMA1_MASK: - case TSDEV_DMA2_MASK: - return NoFault; - case TSDEV_TMR0_DATA: - pitimer.counter0.write(data); - return NoFault; - case TSDEV_TMR1_DATA: - pitimer.counter1.write(data); - return NoFault; - case TSDEV_TMR2_DATA: - pitimer.counter2.write(data); - return NoFault; - case TSDEV_TMR_CTRL: - pitimer.writeControl(data); - return NoFault; - case TSDEV_RTC_ADDR: - rtc.writeAddr(data); - return NoFault; - case TSDEV_KBD: - return NoFault; - case TSDEV_RTC_DATA: - rtc.writeData(data); - return NoFault; - case TSDEV_CTRL_PORTB: - // System Control Port B not implemented - return NoFault; - default: - panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data); + switch(daddr) { + case TSDEV_PIC1_MASK: + mask1 = ~(val); + if ((picr & mask1) && !picInterrupting) { + picInterrupting = true; + tsunami->cchip->postDRIR(55); + DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); } - case sizeof(uint16_t): - case sizeof(uint32_t): - case sizeof(uint64_t): + if ((!(picr & mask1)) && picInterrupting) { + picInterrupting = false; + tsunami->cchip->clearDRIR(55); + DPRINTF(Tsunami, "clearing pic interrupt\n"); + } + break; + case TSDEV_PIC2_MASK: + mask2 = val; + //PIC2 Not implemented to interrupt + break; + case TSDEV_PIC1_ACK: + // clear the interrupt on the PIC + picr &= ~(1 << (val & 0xF)); + if (!(picr & mask1)) + tsunami->cchip->clearDRIR(55); + break; + case TSDEV_DMA1_MODE: + mode1 = val; + break; + case TSDEV_DMA2_MODE: + mode2 = val; + break; + case TSDEV_TMR0_DATA: + pitimer.counter0.write(val); + break; + case TSDEV_TMR1_DATA: + pitimer.counter1.write(val); + break; + case TSDEV_TMR2_DATA: + pitimer.counter2.write(val); + break; + case TSDEV_TMR_CTRL: + pitimer.writeControl(val); + break; + case TSDEV_RTC_ADDR: + rtc.writeAddr(val); + break; + case TSDEV_RTC_DATA: + rtc.writeData(val); + break; + case TSDEV_KBD: + case TSDEV_DMA1_CMND: + case TSDEV_DMA2_CMND: + case TSDEV_DMA1_MMASK: + case TSDEV_DMA2_MMASK: + case TSDEV_PIC2_ACK: + case TSDEV_DMA1_RESET: + case TSDEV_DMA2_RESET: + case TSDEV_DMA1_MASK: + case TSDEV_DMA2_MASK: + case TSDEV_CTRL_PORTB: + break; default: - panic("I/O Write - invalid size - va %#x size %d\n", - req->vaddr, req->size); + panic("I/O Write - va%#x size %d data %#x\n", pkt.addr, pkt.size, val); } - - return NoFault; + pkt.result = Success; + return pioDelay; } void @@ -647,12 +625,6 @@ TsunamiIO::clearPIC(uint8_t bitvector) } } -Tick -TsunamiIO::cacheAccess(MemReqPtr &req) -{ - return curTick + pioLatency; -} - void TsunamiIO::serialize(ostream &os) { @@ -687,34 +659,40 @@ TsunamiIO::unserialize(Checkpoint *cp, const string §ion) BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) - SimObjectParam<Tsunami *> tsunami; - Param<time_t> time; - SimObjectParam<MemoryController *> mmu; - Param<Addr> addr; - SimObjectParam<Bus*> pio_bus; + Param<Addr> pio_addr; Param<Tick> pio_latency; - SimObjectParam<HierParams *> hier; Param<Tick> frequency; + SimObjectParam<Platform *> platform; + SimObjectParam<System *> system; + Param<time_t> time; + SimObjectParam<Tsunami *> tsunami; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO) - INIT_PARAM(tsunami, "Tsunami"), + INIT_PARAM(pio_addr, "Device Address"), + INIT_PARAM(pio_latency, "Programmed IO latency"), + INIT_PARAM(frequency, "clock interrupt frequency"), + INIT_PARAM(platform, "platform"), + INIT_PARAM(system, "system object"), INIT_PARAM(time, "System time to use (0 for actual time"), - INIT_PARAM(mmu, "Memory Controller"), - INIT_PARAM(addr, "Device Address"), - INIT_PARAM(pio_bus, "The IO Bus to attach to"), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), - INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams), - INIT_PARAM(frequency, "clock interrupt frequency") + INIT_PARAM(tsunami, "Tsunami") END_INIT_SIM_OBJECT_PARAMS(TsunamiIO) CREATE_SIM_OBJECT(TsunamiIO) { - return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier, - pio_bus, pio_latency, frequency); + TsunamiIO::Params *p = new TsunamiIO::Params; + p->frequency = frequency; + p->name = getInstanceName(); + p->pio_addr = pio_addr; + p->pio_delay = pio_latency; + p->platform = platform; + p->system = system; + p->init_time = time; + p->tsunami = tsunami; + return new TsunamiIO(p); } REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO) diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index b024ecd14..c37f3aa16 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -38,21 +38,13 @@ #include "dev/tsunami.hh" #include "sim/eventq.hh" -class MemoryController; - /** * Tsunami I/O device is a catch all for all the south bridge stuff we care * to implement. */ -class TsunamiIO : public PioDevice +class TsunamiIO : public BasicPioDevice { private: - /** The base address of this device */ - Addr addr; - - /** The size of mappad from the above address */ - static const Addr size = 0xff; - struct tm tm; protected: @@ -120,10 +112,10 @@ class TsunamiIO : public PioDevice void set_time(time_t t); /** RTC address port: write address of RTC RAM data to access */ - void writeAddr(const uint8_t *data); + void writeAddr(const uint8_t data); /** RTC write data */ - void writeData(const uint8_t *data); + void writeData(const uint8_t data); /** RTC read data */ void readData(uint8_t *data); @@ -218,7 +210,7 @@ class TsunamiIO : public PioDevice void read(uint8_t *data); /** Write a count byte */ - void write(const uint8_t *data); + void write(const uint8_t data); /** Is the output high? */ bool outputHigh(); @@ -254,7 +246,7 @@ class TsunamiIO : public PioDevice PITimer(const std::string &name); /** Write control word */ - void writeControl(const uint8_t* data); + void writeControl(const uint8_t data); /** * Serialize this object to the given output stream. @@ -289,8 +281,6 @@ class TsunamiIO : public PioDevice /** Is the pic interrupting right now or not. */ bool picInterrupting; - Tick clockInterval; - /** A pointer to the Tsunami device which be belong to */ Tsunami *tsunami; @@ -312,33 +302,24 @@ class TsunamiIO : public PioDevice */ Tick frequency() const; + struct Params : public BasicPioDevice::Params + { + Tick frequency; + Tsunami *tsunami; + time_t init_time; + }; + protected: + const Params *params() const { return (const Params*)_params; } + + public: /** * Initialize all the data for devices supported by Tsunami I/O. - * @param name name of this device. - * @param t pointer back to the Tsunami object that we belong to. - * @param init_time Time (as in seconds since 1970) to set RTC to. - * @param a address we are mapped at. - * @param mmu pointer to the memory controller that sends us events. + * @param p pointer to Params struct */ - TsunamiIO(const std::string &name, Tsunami *t, time_t init_time, - Addr a, MemoryController *mmu, HierParams *hier, Bus *pio_bus, - Tick pio_latency, Tick ci); + TsunamiIO(Params *p); - /** - * Process a read to one of the devices we are emulating. - * @param req Contains the address to read from. - * @param data A pointer to write the read data to. - * @return The fault condition of the access. - */ - virtual Fault read(MemReqPtr &req, uint8_t *data); - - /** - * Process a write to one of the devices we emulate. - * @param req Contains the address to write to. - * @param data The data to write. - * @return The fault condition of the access. - */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Tick read(Packet &pkt); + virtual Tick write(Packet &pkt); /** * Post an PIC interrupt to the CPU via the CChip @@ -365,7 +346,6 @@ class TsunamiIO : public PioDevice */ virtual void unserialize(Checkpoint *cp, const std::string §ion); - Tick cacheAccess(MemReqPtr &req); }; #endif // __DEV_TSUNAMI_IO_HH__ diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index 202076754..66144b816 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -34,16 +34,11 @@ #include <string> #include <vector> -#include "arch/alpha/ev5.hh" #include "base/trace.hh" #include "dev/tsunami_pchip.hh" #include "dev/tsunamireg.h" #include "dev/tsunami.hh" -#include "mem/bus/bus.hh" -#include "mem/bus/pio_interface.hh" -#include "mem/bus/pio_interface_impl.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +#include "mem/packet.hh" #include "sim/builder.hh" #include "sim/system.hh" @@ -51,12 +46,10 @@ using namespace std; //Should this be AlphaISA? using namespace TheISA; -TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, - Bus *pio_bus, Tick pio_latency) - : PioDevice(name, t), addr(a), tsunami(t) +TsunamiPChip::TsunamiPChip(Params *p) +: BasicPioDevice(p) { - mmu->add_child(this, RangeSize(addr, size)); + pioSize = 0xfff; for (int i = 0; i < 4; i++) { wsba[i] = 0; @@ -64,195 +57,180 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, tba[i] = 0; } - if (pio_bus) { - pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, - &TsunamiPChip::cacheAccess); - pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * pio_bus->clockRate; - } - - // initialize pchip control register pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36); //Set back pointer in tsunami - tsunami->pchip = this; + p->tsunami->pchip = this; } -Fault -TsunamiPChip::read(MemReqPtr &req, uint8_t *data) +Tick +TsunamiPChip::read(Packet &pkt) { - DPRINTF(Tsunami, "read va=%#x size=%d\n", - req->vaddr, req->size); - - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; - - switch (req->size) { - - case sizeof(uint64_t): - switch(daddr) { - case TSDEV_PC_WSBA0: - *(uint64_t*)data = wsba[0]; - return NoFault; - case TSDEV_PC_WSBA1: - *(uint64_t*)data = wsba[1]; - return NoFault; - case TSDEV_PC_WSBA2: - *(uint64_t*)data = wsba[2]; - return NoFault; - case TSDEV_PC_WSBA3: - *(uint64_t*)data = wsba[3]; - return NoFault; - case TSDEV_PC_WSM0: - *(uint64_t*)data = wsm[0]; - return NoFault; - case TSDEV_PC_WSM1: - *(uint64_t*)data = wsm[1]; - return NoFault; - case TSDEV_PC_WSM2: - *(uint64_t*)data = wsm[2]; - return NoFault; - case TSDEV_PC_WSM3: - *(uint64_t*)data = wsm[3]; - return NoFault; - case TSDEV_PC_TBA0: - *(uint64_t*)data = tba[0]; - return NoFault; - case TSDEV_PC_TBA1: - *(uint64_t*)data = tba[1]; - return NoFault; - case TSDEV_PC_TBA2: - *(uint64_t*)data = tba[2]; - return NoFault; - case TSDEV_PC_TBA3: - *(uint64_t*)data = tba[3]; - return NoFault; - case TSDEV_PC_PCTL: - *(uint64_t*)data = pctl; - return NoFault; - case TSDEV_PC_PLAT: - panic("PC_PLAT not implemented\n"); - case TSDEV_PC_RES: - panic("PC_RES not implemented\n"); - case TSDEV_PC_PERROR: - *(uint64_t*)data = 0x00; - return NoFault; - case TSDEV_PC_PERRMASK: - *(uint64_t*)data = 0x00; - return NoFault; - case TSDEV_PC_PERRSET: - panic("PC_PERRSET not implemented\n"); - case TSDEV_PC_TLBIV: - panic("PC_TLBIV not implemented\n"); - case TSDEV_PC_TLBIA: - *(uint64_t*)data = 0x00; // shouldn't be readable, but linux - return NoFault; - case TSDEV_PC_PMONCTL: - panic("PC_PMONCTL not implemented\n"); - case TSDEV_PC_PMONCNT: - panic("PC_PMONCTN not implemented\n"); - default: - panic("Default in PChip Read reached reading 0x%x\n", daddr); - - } // uint64_t - - break; - case sizeof(uint32_t): - case sizeof(uint16_t): - case sizeof(uint8_t): + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + + pkt.time = curTick + pioDelay; + Addr daddr = (pkt.addr - pioAddr) >> 6;; + + uint64_t *data64; + + if (!pkt.data) { + data64 = new uint64_t; + pkt.data = (uint8_t*)data64; + } else + data64 = (uint64_t*)pkt.data; + + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size); + + switch(daddr) { + case TSDEV_PC_WSBA0: + *data64 = wsba[0]; + break; + case TSDEV_PC_WSBA1: + *data64 = wsba[1]; + break; + case TSDEV_PC_WSBA2: + *data64 = wsba[2]; + break; + case TSDEV_PC_WSBA3: + *data64 = wsba[3]; + break; + case TSDEV_PC_WSM0: + *data64 = wsm[0]; + break; + case TSDEV_PC_WSM1: + *data64 = wsm[1]; + break; + case TSDEV_PC_WSM2: + *data64 = wsm[2]; + break; + case TSDEV_PC_WSM3: + *data64 = wsm[3]; + break; + case TSDEV_PC_TBA0: + *data64 = tba[0]; + break; + case TSDEV_PC_TBA1: + *data64 = tba[1]; + break; + case TSDEV_PC_TBA2: + *data64 = tba[2]; + break; + case TSDEV_PC_TBA3: + *data64 = tba[3]; + break; + case TSDEV_PC_PCTL: + *data64 = pctl; + break; + case TSDEV_PC_PLAT: + panic("PC_PLAT not implemented\n"); + case TSDEV_PC_RES: + panic("PC_RES not implemented\n"); + case TSDEV_PC_PERROR: + *data64 = 0x00; + break; + case TSDEV_PC_PERRMASK: + *data64 = 0x00; + break; + case TSDEV_PC_PERRSET: + panic("PC_PERRSET not implemented\n"); + case TSDEV_PC_TLBIV: + panic("PC_TLBIV not implemented\n"); + case TSDEV_PC_TLBIA: + *data64 = 0x00; // shouldn't be readable, but linux + break; + case TSDEV_PC_PMONCTL: + panic("PC_PMONCTL not implemented\n"); + case TSDEV_PC_PMONCNT: + panic("PC_PMONCTN not implemented\n"); default: - panic("invalid access size(?) for tsunami register!\n\n"); + panic("Default in PChip Read reached reading 0x%x\n", daddr); } - DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); + pkt.result = Success; + return pioDelay; - return NoFault; } -Fault -TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) +Tick +TsunamiPChip::write(Packet &pkt) { - DPRINTF(Tsunami, "write - va=%#x size=%d \n", - req->vaddr, req->size); - - Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; - - switch (req->size) { - - case sizeof(uint64_t): - switch(daddr) { - case TSDEV_PC_WSBA0: - wsba[0] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_WSBA1: - wsba[1] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_WSBA2: - wsba[2] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_WSBA3: - wsba[3] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_WSM0: - wsm[0] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_WSM1: - wsm[1] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_WSM2: - wsm[2] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_WSM3: - wsm[3] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_TBA0: - tba[0] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_TBA1: - tba[1] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_TBA2: - tba[2] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_TBA3: - tba[3] = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_PCTL: - pctl = *(uint64_t*)data; - return NoFault; - case TSDEV_PC_PLAT: - panic("PC_PLAT not implemented\n"); - case TSDEV_PC_RES: - panic("PC_RES not implemented\n"); - case TSDEV_PC_PERROR: - return NoFault; - case TSDEV_PC_PERRMASK: - panic("PC_PERRMASK not implemented\n"); - case TSDEV_PC_PERRSET: - panic("PC_PERRSET not implemented\n"); - case TSDEV_PC_TLBIV: - panic("PC_TLBIV not implemented\n"); - case TSDEV_PC_TLBIA: - return NoFault; // value ignored, supposted to invalidate SG TLB - case TSDEV_PC_PMONCTL: - panic("PC_PMONCTL not implemented\n"); - case TSDEV_PC_PMONCNT: - panic("PC_PMONCTN not implemented\n"); - default: - panic("Default in PChip Read reached reading 0x%x\n", daddr); - - } // uint64_t - - break; - case sizeof(uint32_t): - case sizeof(uint16_t): - case sizeof(uint8_t): - default: - panic("invalid access size(?) for tsunami register!\n\n"); - } - - DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); - - return NoFault; + pkt.time = curTick + pioDelay; + + assert(pkt.result == Unknown); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + Addr daddr = (pkt.addr - pioAddr) >> 6; + + uint64_t data64 = *(uint64_t *)pkt.data; + assert(pkt.size == sizeof(uint64_t)); + + DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size); + + switch(daddr) { + case TSDEV_PC_WSBA0: + wsba[0] = data64; + break; + case TSDEV_PC_WSBA1: + wsba[1] = data64; + break; + case TSDEV_PC_WSBA2: + wsba[2] = data64; + break; + case TSDEV_PC_WSBA3: + wsba[3] = data64; + break; + case TSDEV_PC_WSM0: + wsm[0] = data64; + break; + case TSDEV_PC_WSM1: + wsm[1] = data64; + break; + case TSDEV_PC_WSM2: + wsm[2] = data64; + break; + case TSDEV_PC_WSM3: + wsm[3] = data64; + break; + case TSDEV_PC_TBA0: + tba[0] = data64; + break; + case TSDEV_PC_TBA1: + tba[1] = data64; + break; + case TSDEV_PC_TBA2: + tba[2] = data64; + break; + case TSDEV_PC_TBA3: + tba[3] = data64; + break; + case TSDEV_PC_PCTL: + pctl = data64; + break; + case TSDEV_PC_PLAT: + panic("PC_PLAT not implemented\n"); + case TSDEV_PC_RES: + panic("PC_RES not implemented\n"); + case TSDEV_PC_PERROR: + break; + case TSDEV_PC_PERRMASK: + panic("PC_PERRMASK not implemented\n"); + case TSDEV_PC_PERRSET: + panic("PC_PERRSET not implemented\n"); + case TSDEV_PC_TLBIV: + panic("PC_TLBIV not implemented\n"); + case TSDEV_PC_TLBIA: + break; // value ignored, supposted to invalidate SG TLB + case TSDEV_PC_PMONCTL: + panic("PC_PMONCTL not implemented\n"); + case TSDEV_PC_PMONCNT: + panic("PC_PMONCTN not implemented\n"); + default: + panic("Default in PChip write reached reading 0x%x\n", daddr); + + } // uint64_t + + pkt.result = Success; + return pioDelay; } #define DMA_ADDR_MASK ULL(0x3ffffffff) @@ -312,10 +290,7 @@ TsunamiPChip::translatePciToDma(Addr busAddr) baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13); pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10); - memcpy((void *)&pteEntry, - tsunami->system-> - physmem->dma_addr(pteAddr, sizeof(uint64_t)), - sizeof(uint64_t)); + pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t)); dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff)); @@ -352,38 +327,37 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_ARRAY(tba, 4); } -Tick -TsunamiPChip::cacheAccess(MemReqPtr &req) -{ - return curTick + pioLatency; -} BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) - SimObjectParam<Tsunami *> tsunami; - SimObjectParam<MemoryController *> mmu; - Param<Addr> addr; - SimObjectParam<Bus*> pio_bus; + Param<Addr> pio_addr; Param<Tick> pio_latency; - SimObjectParam<HierParams *> hier; + SimObjectParam<Platform *> platform; + SimObjectParam<System *> system; + SimObjectParam<Tsunami *> tsunami; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) - INIT_PARAM(tsunami, "Tsunami"), - INIT_PARAM(mmu, "Memory Controller"), - INIT_PARAM(addr, "Device Address"), - INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), - INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) + INIT_PARAM(pio_addr, "Device Address"), + INIT_PARAM(pio_latency, "Programmed IO latency"), + INIT_PARAM(platform, "platform"), + INIT_PARAM(system, "system object"), + INIT_PARAM(tsunami, "Tsunami") END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) CREATE_SIM_OBJECT(TsunamiPChip) { - return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, - pio_bus, pio_latency); + TsunamiPChip::Params *p = new TsunamiPChip::Params; + p->name = getInstanceName(); + p->pio_addr = pio_addr; + p->pio_delay = pio_latency; + p->platform = platform; + p->system = system; + p->tsunami = tsunami; + return new TsunamiPChip(p); } REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip) diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh index c1d95431b..2f3e8f078 100644 --- a/dev/tsunami_pchip.hh +++ b/dev/tsunami_pchip.hh @@ -37,28 +37,12 @@ #include "base/range.hh" #include "dev/io_device.hh" -class MemoryController; - /** * A very simple implementation of the Tsunami PCI interface chips. */ -class TsunamiPChip : public PioDevice +class TsunamiPChip : public BasicPioDevice { - private: - /** The base address of this device */ - Addr addr; - - /** The size of mappad from the above address */ - static const Addr size = 0xfff; - protected: - /** - * pointer to the tsunami object. - * This is our access to all the other tsunami - * devices. - */ - Tsunami *tsunami; - /** Pchip control register */ uint64_t pctl; @@ -72,18 +56,19 @@ class TsunamiPChip : public PioDevice uint64_t tba[4]; public: + struct Params : public BasicPioDevice::Params + { + Tsunami *tsunami; + }; + protected: + const Params *params() const { return (const Params*)_params; } + + public: /** * Register the PChip with the mmu and init all wsba, wsm, and tba to 0 - * @param name the name of thes device - * @param t a pointer to the tsunami device - * @param a the address which we respond to - * @param mmu the mmu we are to register with - * @param hier object to store parameters universal the device hierarchy - * @param bus The bus that this device is attached to + * @param p pointer to the parameters struct */ - TsunamiPChip(const std::string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, Bus *pio_bus, - Tick pio_latency); + TsunamiPChip(Params *p); /** * Translate a PCI bus address to a memory address for DMA. @@ -93,21 +78,8 @@ class TsunamiPChip : public PioDevice */ Addr translatePciToDma(Addr busAddr); - /** - * Process a read to the PChip. - * @param req Contains the address to read from. - * @param data A pointer to write the read data to. - * @return The fault condition of the access. - */ - virtual Fault read(MemReqPtr &req, uint8_t *data); - - /** - * Process a write to the PChip. - * @param req Contains the address to write to. - * @param data The data to write. - * @return The fault condition of the access. - */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Tick read(Packet &pkt); + virtual Tick write(Packet &pkt); /** * Serialize this object to the given output stream. @@ -121,13 +93,6 @@ class TsunamiPChip : public PioDevice * @param section The section name of this object */ virtual void unserialize(Checkpoint *cp, const std::string §ion); - - /** - * Return how long this access will take. - * @param req the memory request to calcuate - * @return Tick when the request is done - */ - Tick cacheAccess(MemReqPtr &req); }; #endif // __TSUNAMI_PCHIP_HH__ diff --git a/dev/uart8250.cc b/dev/uart8250.cc index bbb42c065..7e2f9d51f 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -111,7 +111,7 @@ Tick Uart8250::read(Packet &pkt) { assert(pkt.result == Unknown); - assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); assert(pkt.size == 1); pkt.time = curTick + pioDelay; @@ -189,7 +189,10 @@ Uart8250::read(Packet &pkt) panic("Tried to access a UART port that doesn't exist\n"); break; } - +/* uint32_t d32 = *data; + DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32); +*/ + pkt.result = Success; return pioDelay; } @@ -269,6 +272,7 @@ Uart8250::write(Packet &pkt) panic("Tried to access a UART port that doesn't exist\n"); break; } + pkt.result = Success; return pioDelay; } @@ -336,7 +340,7 @@ Uart8250::unserialize(Checkpoint *cp, const std::string §ion) BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250) - Param<Addr> addr; + Param<Addr> pio_addr; Param<Tick> pio_latency; SimObjectParam<Platform *> platform; SimObjectParam<SimConsole *> sim_console; @@ -346,7 +350,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(Uart8250) BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250) - INIT_PARAM(addr, "Device Address"), + INIT_PARAM(pio_addr, "Device Address"), INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), INIT_PARAM(platform, "platform"), INIT_PARAM(sim_console, "The Simulator Console"), @@ -358,7 +362,7 @@ CREATE_SIM_OBJECT(Uart8250) { Uart8250::Params *p = new Uart8250::Params; p->name = getInstanceName(); - p->pio_addr = addr; + p->pio_addr = pio_addr; p->pio_delay = pio_latency; p->platform = platform; p->cons = sim_console; |